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([148.69.202.102]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-486f8b0bc58sm16135905e9.3.2026.03.18.11.52.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Mar 2026 11:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1773859978; x=1774464778; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MyLex6OTnYvy/DWccP0n2Mw9tvmu2JJXYlF6lIdz31c=; b=HA8Z+eM0i233D6Jxws26wt/4pG6VFAYoyHO9jmnKd/XB/XY5KVINWyiGui+vMmoBIS U2jqGtuG7Vx6STq5KAyKA6ZpDwLzd4JEUuYB2Ow8nqM+ter1LJOa8HyDDargszio8gRk m4W9JUHT0zPkJb/ChZ7VrcX9N3Jvw66QKFUGws4XkKMiFLh2CvK2W1lbnf9/wiiSbwOU iRRhyRPPPy3Rr4GNjrkN4wdXNfZe1XqQLUIpmi3ZX+DBfjKHuV9OElwNadpKhHCmkDDr fjrdtYlBTAjJGo8G94ntRnn+hLLM5FriM4Xm1Y7N5WwSsJpnkoQm3CfF7xzxuRnuvDBO s3NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1773859978; x=1774464778; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=MyLex6OTnYvy/DWccP0n2Mw9tvmu2JJXYlF6lIdz31c=; b=pFv0ttLpH0RvxA3CVymodJ/rsXZAViCvbkYUB6v5C/lbm+RQZbYdWeHASjOfQyDjtH CMndRJQBbppA1k2ZyDJVFtWYOTOG48fd4M3a338n/ZrMONNomEGHUlY4oFZHJk2+MpF/ wurbhPXHcvywaeBE2LFlULnjL2yJKj8Qp5sb0fsWoi+2XUv5bVKcanuf5jz+UzAM3xqS LH8lmxyBBPhFsyFDTsykbisYp/zgOuR+yTXuBeiex4qLswQoXr5IMX3Ufhldt87iCxxd nffXsiaJrsxsXvtP9j1364P9F+eZl1p3CAcmiu+YErOrXbCBo6ueJop1U3D/nzh+S8zn jCfg== X-Gm-Message-State: AOJu0Yw16QfKy6o/nG0f5nK+2X4uWcL8+9cXvjzsEWLr+fQdsEs4sNSt PliHHyew/BbEvnJJWrPEFpGBavEc2zV/be3Cao25aKu0z+I5/Evp1VBU1WfYUq52fuU= X-Gm-Gg: ATEYQzwQgZvrercQchcYu8VJmf+9Z61RFzAE4qQN/JC2BBjy3PKgVtt0g4LPA58foSV DDHoCR+c8P2vdjoLBZtTuZxTyiFaP9qrMaAhrfb/eYAbSuF0d9YFpWJjbIMBEk25v42ZrC6I8+i aProFSfi0UIbtd6/EI23GQRyGJmIpPqlI6+Pjn4N8aDGz8/1j/OsIiDqzWaTp332EGHHIFC4950 OOXTps4Q3NzYi67C9uQDjdRQKN3v9C52XI52j+UtQzTg5jVhyvGk86ow8PDsDvMWbPGZEKnMQ5k 1MB9msEtCoyAd8vteVB9SShdI6Ds3DdWOq0c4YK+cOg+S8L79OMSM8vhREeio28WAfMNPKMRwEZ jd53oMvAYekOzVfD7hW0w9P4DNwge2dt8fA94ticp2vimf1PdXkzXHIn5VYkLYDuF6eLRKeGurV EM4wZmsOkJaRQ9bPk+te62FtPM/IKUlcFe+OMyVuae46CWVEZimuUJUS1iDkBceGuYhwhbws51b CNJTU4JfRth6J82zE1JymcwUBBKotG6EchtGfk= X-Received: by 2002:a05:600c:3544:b0:485:3e00:944a with SMTP id 5b1f17b1804b1-486f8b35605mr11473145e9.9.1773859977695; Wed, 18 Mar 2026 11:52:57 -0700 (PDT) From: luisccc To: qemu-devel@nongnu.org Cc: luisccc , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [RFC PATCH 1/6] target/riscv: Add SPMP infrastructure Date: Wed, 18 Mar 2026 18:52:31 +0000 Message-ID: <20260318185238.99143-2-luisccunha8@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318185238.99143-1-luisccunha8@gmail.com> References: <20260318185238.99143-1-luisccunha8@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=luisccunha8@gmail.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Wed, 18 Mar 2026 15:44:14 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773863113757154100 Introduce the initial infrastructure required for the RISC-V S-mode Physica= l Memory Protection (SPMP) implementation. This patch adds the SPMP source files, integrates them into the build syste= m, and introduces the CPU state and configuration fields required by subseq= uent patches. No SPMP checks are enforced yet. Signed-off-by: Luis Cunha --- target/riscv/cpu.h | 6 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/meson.build | 1 + target/riscv/spmp.c | 512 ++++++++++++++++++++++++++++++ target/riscv/spmp.h | 83 +++++ 5 files changed, 603 insertions(+) create mode 100644 target/riscv/spmp.c create mode 100644 target/riscv/spmp.h diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..c265098324 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -178,8 +178,11 @@ extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implie= d_rules[]; #define OLD_MAX_RISCV_PMPS (16) #define MIN_RISCV_PMP_GRANULARITY 4 =20 +#define MAX_RISCV_SPMPS (64) + #if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#include "spmp.h" #include "debug.h" #endif =20 @@ -442,6 +445,9 @@ struct CPUArchState { pmp_table_t pmp_state; target_ulong mseccfg; =20 + /* S-mode Physical Memory Protection */ + spmp_table_t spmp_state; + /* trigger module */ target_ulong trigger_cur; target_ulong tdata1[RV_MAX_TRIGGERS]; diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 70ec650abf..72d417c241 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -156,6 +156,7 @@ BOOL_FIELD(ext_xmipslsp) =20 BOOL_FIELD(mmu) BOOL_FIELD(pmp) +BOOL_FIELD(spmp) BOOL_FIELD(debug) BOOL_FIELD(misa_w) =20 diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 3842c7c1a8..d03f3a7826 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -34,6 +34,7 @@ riscv_system_ss =3D ss.source_set() riscv_system_ss.add(files( 'arch_dump.c', 'pmp.c', + 'spmp.c', 'debug.c', 'monitor.c', 'machine.c', diff --git a/target/riscv/spmp.c b/target/riscv/spmp.c new file mode 100644 index 0000000000..85c5259b33 --- /dev/null +++ b/target/riscv/spmp.c @@ -0,0 +1,512 @@ +/* + * QEMU RISC-V SPMP (S-mode Physical Memory Protection) + * + * Author: + * Lu=C3=ADs Cunha + * + * Based on an earlier SPMP prototype by: + * Bicheng Yang + * Dong Du + * + * This provides a RISC-V S-mode Physical Memory Protection interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu_bits.h" +#include "trace.h" +#include "exec/target_page.h" + +/* + * Accessor method to extract address matching type 'a field' from cfg reg + */ +uint8_t spmp_get_a_field(uint8_t cfg) +{ + uint8_t a =3D cfg >> 3; + return a & 0x3; +} + +/* + * Check whether mstatus.sum is set. + */ +static inline int sum_is_set(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_SUM) { + return 1; + } + + return 0; +} + +void spmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) +{ + /* + * aaaa...aaa0 8-byte NAPOT range + * aaaa...aa01 16-byte NAPOT range + * aaaa...a011 32-byte NAPOT range + * ... + * aa01...1111 2^XLEN-byte NAPOT range + * a011...1111 2^(XLEN+1)-byte NAPOT range + * 0111...1111 2^(XLEN+2)-byte NAPOT range + * 1111...1111 Reserved + */ + a =3D (a << 2) | 0x3; + *sa =3D a & (a + 1); + *ea =3D a | (a + 1); +} + +static void spmp_update_rule_addr(CPURISCVState *env, uint32_t spmp_index) +{ + uint8_t this_cfg =3D env->spmp_state.spmp[spmp_index].cfg_reg; + target_ulong this_addr =3D env->spmp_state.spmp[spmp_index].addr_reg; + target_ulong prev_addr =3D 0u; + target_ulong sa =3D 0u; + target_ulong ea =3D 0u; + + if (spmp_index >=3D 1u) { + prev_addr =3D env->spmp_state.spmp[spmp_index - 1].addr_reg; + } + + switch (spmp_get_a_field(this_cfg)) { + case SPMP_AMATCH_OFF: + sa =3D 0u; + ea =3D -1; + break; + + case SPMP_AMATCH_TOR: + sa =3D prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea =3D (this_addr << 2) - 1u; + break; + + case SPMP_AMATCH_NA4: + sa =3D this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea =3D (sa + 4u) - 1u; + break; + + case SPMP_AMATCH_NAPOT: + spmp_decode_napot(this_addr, &sa, &ea); + break; + + default: + sa =3D 0u; + ea =3D 0u; + break; + } + + env->spmp_state.addr[spmp_index].sa =3D sa; + env->spmp_state.addr[spmp_index].ea =3D ea; +} + +static void spmp_update_rule_nums(CPURISCVState *env) +{ + int i; + + env->spmp_state.num_active_rules =3D 0; + for (i =3D 0; i < MAX_RISCV_SPMPS; i++) { + const uint8_t a_field =3D + spmp_get_a_field(env->spmp_state.spmp[i].cfg_reg); + if (SPMP_AMATCH_OFF !=3D a_field) { + env->spmp_state.num_active_rules++; + } + } +} + +/* + * Convert cfg/addr reg values here into simple 'sa' --> start address and= 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a spmp rule is called often, so optimise that one + */ +static void spmp_update_rule(CPURISCVState *env, uint32_t spmp_index) +{ + spmp_update_rule_addr(env, spmp_index); + spmp_update_rule_nums(env); +} + +static uint8_t spmp_is_in_range(CPURISCVState *env, int spmp_index, + target_ulong addr) +{ + if ((addr >=3D env->spmp_state.addr[spmp_index].sa) + && (addr <=3D env->spmp_state.addr[spmp_index].ea)) { + return 1; + } + + return 0; +} + +static bool spmp_get_spmpen_bit(CPURISCVState *env, int index) +{ + return true; +} + +/* + * Check if the address has required RWX privs when no SPMP entry is match= ed. + */ +static bool spmp_hart_has_privs_default(CPURISCVState *env, target_ulong a= ddr, + spmp_priv_t *allowed_privs, + target_ulong mode) +{ + bool ret; + mode =3D env->virt_enabled ? PRV_U : mode; + + if ((!riscv_cpu_cfg(env)->spmp) || !(mode =3D=3D PRV_U)) { + /* + * The SPMP proposal states three circumstances that the access + * is allowed: + * 1. The HW does not implement any SPMP entry. + * 2. If the effective privilege mode of the access is S and no SP= MP + * entry matches + * 3. The access mode is M. + */ + ret =3D true; + *allowed_privs =3D SPMP_READ | SPMP_WRITE | SPMP_EXEC; + } else { + /* + * U-mode is not allowed to succeed if they don't match a rule, + * but there are rules. We've checked for those rules earlier in t= his + * function. + */ + ret =3D false; + *allowed_privs =3D 0; + } + + return ret; +} + + +/* + * Public Interface + */ + +/* + * Check if the address has required RWX privs to complete desired operati= on + */ +bool spmp_hart_has_privs(CPURISCVState *env, target_ulong addr, + target_ulong size, spmp_priv_t privs, spmp_priv_t *allowed_privs, + target_ulong mode) +{ + int i =3D 0; + int ret =3D -1; + int spmp_size =3D 0; + target_ulong s =3D 0; + target_ulong e =3D 0; + bool spmpen_en =3D false; + + /* If it is either VS or VU mode, we treat it as U mode */ + mode =3D env->virt_enabled ? PRV_U : mode; + + /* Short cut for M-mode access */ + if (mode =3D=3D PRV_M) { + *allowed_privs =3D SPMP_READ | SPMP_WRITE | SPMP_EXEC; + return true; + } + + /* Short cut if no rules */ + if (env->spmp_state.num_active_rules =3D=3D 0) { + return spmp_hart_has_privs_default(env, addr, allowed_privs, mode); + } + + if (size =3D=3D 0) { + if (riscv_cpu_cfg(env)->mmu) { + /* + * If size is unknown (0), assume that all bytes + * from addr to the end of the page will be accessed. + */ + spmp_size =3D -(addr | TARGET_PAGE_MASK); + } else { + spmp_size =3D sizeof(target_ulong); + } + } else { + spmp_size =3D size; + } + + /* It depends on mpmpdeleg */ + for (i =3D 0; i < env->spmp_state.num_deleg_rules; i++) { + s =3D spmp_is_in_range(env, i, addr); + e =3D spmp_is_in_range(env, i, addr + spmp_size - 1); + spmpen_en =3D spmp_get_spmpen_bit(env, i); + + /* partially inside */ + if ((s + e) =3D=3D 1) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: spmp violation - access is partially inside= \n", + __func__); + ret =3D 0; + break; + } + + /* fully inside */ + const uint8_t a_field =3D + spmp_get_a_field(env->spmp_state.spmp[i].cfg_reg); + + /* + * Convert the SPMP permissions to match the truth table in the + * SPMP spec. + */ + const uint8_t spmp_operation =3D + (env->spmp_state.spmp[i].cfg_reg & SPMP_EX= EC) + | (env->spmp_state.spmp[i].cfg_reg & SPMP_= WRITE) + | (env->spmp_state.spmp[i].cfg_reg & SPMP_= READ); + + if (((s + e) =3D=3D 2) && (SPMP_AMATCH_OFF !=3D a_field) && spmpen= _en) { + /* + * If the SPMP entry is not off, spmpen bit is set, and the ad= dress + * is in range, do the priv check + */ + + /* Shared not set */ + if (!(env->spmp_state.spmp[i].cfg_reg & SPMP_SHARED)) { + /* + * Deny if: + * S mode access, with SUM not set, and UMODE set. + * U mode access, with UMODE not set. + */ + if ((mode =3D=3D PRV_S && !sum_is_set(env) && + (env->spmp_state.spmp[i].cfg_reg & SPMP_UMODE)) || + (mode =3D=3D PRV_U && + !(env->spmp_state.spmp[i].cfg_reg & SPMP_UMODE))) { + *allowed_privs =3D 0; + } + /* + * EnforceNoX if: + * S mode access, with SUM set, and UMODE set. + * Note: The specification has the table in RWX, the opo= site + * of the order in the cfg reg. + */ + else if (mode =3D=3D PRV_S && sum_is_set(env) && + (env->spmp_state.spmp[i].cfg_reg & SPMP_UMODE)) { + switch (spmp_operation) { + case 0: + case 2: + case 4: + case 6: + *allowed_privs =3D 0; + break; + case 1: + case 5: + *allowed_privs =3D SPMP_READ; + break; + case 3: + case 7: + *allowed_privs =3D SPMP_READ | SPMP_WRITE; + break; + default: + g_assert_not_reached(); + } + } else { + /* Check for reserved configs */ + if (spmp_operation =3D=3D 2 || spmp_operation =3D=3D 6= ) { + *allowed_privs =3D 0; + } else { + /* U mode falls here - Enforce */ + *allowed_privs =3D spmp_operation & 0x7; + } + } + } + /* Set Shared bit */ + else { + if (mode =3D=3D PRV_S) { + /* Check for reserved configs */ + if (spmp_operation =3D=3D 2 || spmp_operation =3D=3D 6= ) { + *allowed_privs =3D 0; + } else { + *allowed_privs =3D spmp_operation & 0x7; + } + } else { + switch (spmp_operation) { + case 0: + case 2: + case 6: + *allowed_privs =3D 0; + break; + case 1: + case 3: + *allowed_privs =3D SPMP_READ; + break; + case 4: + case 7: + *allowed_privs =3D SPMP_EXEC; + break; + case 5: + *allowed_privs =3D SPMP_READ | SPMP_EXEC; + break; + default: + g_assert_not_reached(); + } + } + } + + ret =3D ((privs & *allowed_privs) =3D=3D privs); + break; + } + } + + /* No rule matched */ + if (ret =3D=3D -1) { + return spmp_hart_has_privs_default(env, addr, allowed_privs, mode); + } + + return ret =3D=3D 1 ? true : false; +} + +static bool is_entry_locked(CPURISCVState *env, int index) +{ + uint8_t next_a_field =3D SPMP_AMATCH_TOR; + + /* + * Verify if it is the last entry. + * If not, check if the next entry is TOR type. + * If it is TOR, check if either this or next entry is locked. + */ + if (index < env->spmp_state.num_deleg_rules - 1) { + next_a_field =3D + spmp_get_a_field(env->spmp_state.spmp[index + 1].cfg_r= eg); + + if (next_a_field =3D=3D SPMP_AMATCH_TOR) { + return (env->spmp_state.locked_rules >> index) & 0x1 + || (env->spmp_state.locked_rules >> (index + 1)) & 0x1; + } + } + + /* Otherwise, just check this entry */ + return (env->spmp_state.locked_rules >> index) & 0x1; +} + +/* + * Accessor to set the cfg reg for a specific SPMP/HART + * Bounds checks. + */ +void spmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, + target_ulong val, bool m_mode_access) +{ + bool locked =3D m_mode_access ? false : is_entry_locked(env, reg_index= ); + + /* If within bounds and not locked */ + if (reg_index < env->spmp_state.num_deleg_rules && !locked) { + + env->spmp_state.spmp[reg_index].cfg_reg =3D val; + /* Storing this allows for faster switching with the sspmpen ext */ + env->spmp_state.locked_rules |=3D + ((val & SPMP_LOCK) >> 7 & 0x1) << reg_inde= x; + + spmp_update_rule(env, reg_index); + } else { + if (locked) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ignoring spmpcfg write - locked entry\n", __func_= _); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ignoring spmpcfg write - out of bounds\n", __func= __); + } + } +} + +/* + * Handle a read from a spmpcfg CSR + */ +target_ulong spmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) +{ + if (reg_index < env->spmp_state.num_deleg_rules) { + return env->spmp_state.spmp[reg_index].cfg_reg; + } + + return 0; +} + +/* + * Handle a write to a spmpaddr CSR + */ +void spmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, + target_ulong val, bool m_mode_access) +{ + bool locked =3D m_mode_access ? false : is_entry_locked(env, addr_inde= x); + + /* If within bounds and not locked */ + if (addr_index < env->spmp_state.num_deleg_rules && !locked) { + + env->spmp_state.spmp[addr_index].addr_reg =3D val; + spmp_update_rule(env, addr_index); + } else { + if (locked) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ignoring spmpaddr write - locked entry\n", __func= __); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ignoring spmpaddr write - out of bounds\n", __fun= c__); + } + } +} + +/* + * Handle a read from a spmpaddr CSR + */ +target_ulong spmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) +{ + target_ulong val =3D 0; + + if (addr_index < env->spmp_state.num_deleg_rules) { + val =3D env->spmp_state.spmp[addr_index].addr_reg; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: ignoring spmpaddr read - out of bounds\n", __fu= nc__); + } + + return val; +} + +/* + * Handle a write to the sspmpen CSR + */ +void sspmpen_csr_write(CPURISCVState *env, uint64_t new_val) +{ + uint64_t mask =3D (env->spmp_state.num_deleg_rules =3D=3D MAX_RISCV_SP= MPS) ? + ~0ULL : ((1ULL << env->spmp_state.num_deleg_rules) - 1= ); + + /* If the rule is locked, the bit cannot be changed */ + env->spmp_state.spmpen =3D + (env->spmp_state.spmpen & env->spmp_state.locked_rules= ) | + (new_val & ~env->spmp_state.locked_rules); + env->spmp_state.spmpen &=3D mask; +} + +/* + * Convert SPMP privilege to TLB page privilege. + */ +int spmp_priv_to_page_prot(spmp_priv_t spmp_priv) +{ + int prot =3D 0; + + if (spmp_priv & SPMP_READ) { + prot |=3D PAGE_READ; + } + if (spmp_priv & SPMP_WRITE) { + prot |=3D PAGE_WRITE; + } + if (spmp_priv & SPMP_EXEC) { + prot |=3D PAGE_EXEC; + } + + return prot; +} + +void spmp_unlock_entries(CPURISCVState *env) +{ + /* Reset everything */ + for (int i =3D 0; i < MAX_RISCV_SPMPS; i++) { + env->spmp_state.spmp[i].cfg_reg &=3D ~(SPMP_LOCK | SPMP_AMATCH); + } + + env->spmp_state.locked_rules =3D 0; + env->spmp_state.num_active_rules =3D 0; +} diff --git a/target/riscv/spmp.h b/target/riscv/spmp.h new file mode 100644 index 0000000000..02a05acdf8 --- /dev/null +++ b/target/riscv/spmp.h @@ -0,0 +1,83 @@ +/* + * QEMU RISC-V SPMP (S-mode Physical Memory Protection) + * + * Author: + * Lu=C3=ADs Cunha + * + * Based on an earlier SPMP prototype by: + * Bicheng Yang + * Dong Du + * + * This provides a RISC-V S-mode Physical Memory Protection interface. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + */ + +#ifndef RISCV_SPMP_H +#define RISCV_SPMP_H + + +typedef enum { + SPMP_READ =3D (1 << 0), + SPMP_WRITE =3D (1 << 1), + SPMP_EXEC =3D (1 << 2), + SPMP_AMATCH =3D (3 << 3), + SPMP_LOCK =3D (1 << 7), + SPMP_UMODE =3D (1 << 8), + SPMP_SHARED =3D (1 << 9) +} spmp_priv_t; + +typedef enum { + SPMP_AMATCH_OFF, /* Null (off) */ + SPMP_AMATCH_TOR, /* Top of Range */ + SPMP_AMATCH_NA4, /* Naturally aligned four-byte region */ + SPMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ +} spmp_am_t; + +typedef struct { + target_ulong addr_reg; + uint16_t cfg_reg; +} spmp_entry_t; + +typedef struct { + target_ulong sa; + target_ulong ea; +} spmp_addr_t; + +typedef struct { + spmp_entry_t spmp[MAX_RISCV_SPMPS]; + spmp_addr_t addr[MAX_RISCV_SPMPS]; + + uint8_t num_active_rules; + uint8_t num_deleg_rules; + uint64_t spmpen; + uint64_t locked_rules; +} spmp_table_t; + +void spmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, + target_ulong val, bool m_mode_access); +target_ulong spmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); + +target_ulong spmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); +void spmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, + target_ulong val, bool m_mode_access); + +void sspmpen_csr_write(CPURISCVState *env, uint64_t new_val); + +bool spmp_hart_has_privs(CPURISCVState *env, target_ulong addr, + target_ulong size, spmp_priv_t privs, spmp_priv_t *allowed_privs, + target_ulong mode); +int spmp_priv_to_page_prot(spmp_priv_t spmp_priv); +void spmp_unlock_entries(CPURISCVState *env); + +void spmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea); +uint8_t spmp_get_a_field(uint8_t cfg); + +#endif --=20 2.43.0