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Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v4 7/8] hw/arm/smmuv3-accel: Change OAS property to OasMode Date: Wed, 18 Mar 2026 11:49:06 -0700 Message-ID: <20260318184907.4060030-8-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318184907.4060030-1-nathanc@nvidia.com> References: <20260318184907.4060030-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0140.namprd05.prod.outlook.com (2603:10b6:a03:33d::25) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|CH3PR12MB8233:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f49e25e-b7f2-414e-13a6-08de851f1cbd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859823529158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 OAS property from uint8_t to OasMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 OAS value. Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS bits= ") Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 2 +- hw/arm/smmuv3.c | 16 ++++++++-------- include/hw/arm/smmuv3-common.h | 2 -- include/hw/arm/smmuv3.h | 2 +- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bc6cbfebc2..65c2f44880 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s) } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas =3D=3D SMMU_OAS_48BIT) { + if (s->oas =3D=3D OAS_MODE_48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 79018f8d66..c67819d6f2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1984,6 +1984,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize auto mode is not supported"); return false; } + if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48) { + error_setg(errp, "OAS can only be set to 44 or 48 bits"); + return false; + } =20 if (!s->accel) { if (s->ril =3D=3D ON_OFF_AUTO_OFF) { @@ -1994,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } - if (s->oas !=3D SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } @@ -2012,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); - return false; - } - return true; } =20 @@ -2143,7 +2142,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_0), }; @@ -2180,7 +2179,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " + "supported."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 7f0f992dfd..4609975edf 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -342,8 +342,6 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); =20 -#define SMMU_OAS_44BIT 44 -#define SMMU_OAS_48BIT 48 #define SMMU_IDR5_OAS_44 4 #define SMMU_IDR5_OAS_48 5 =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ddf472493d..82f18eb090 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,7 +72,7 @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; =20 --=20 2.43.0