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Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v4 1/8] hw/arm/smmuv3-accel: Check ATS compatibility between host and guest Date: Wed, 18 Mar 2026 11:49:00 -0700 Message-ID: <20260318184907.4060030-2-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318184907.4060030-1-nathanc@nvidia.com> References: <20260318184907.4060030-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0127.namprd03.prod.outlook.com (2603:10b6:a03:33c::12) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|CH3PR12MB8233:EE_ X-MS-Office365-Filtering-Correlation-Id: 56e5201a-c7e5-4bb3-c66a-08de851f1390 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c105::7; envelope-from=nathanc@nvidia.com; helo=CH4PR04CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859853361154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Compare the host SMMUv3 ATS support bit with the guest SMMUv3 ATS support bit in IDR0 and fail the compatibility check if ATS support is opted as enabled on the guest SMMUv3 when it is not supported on host SMMUv3. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Reviewed-by: Eric Auger Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 17306cd04b..2bb142c47f 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -101,6 +101,12 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); return false; } + /* Check ATS value opted is compatible with Host SMMUv3 */ + if (FIELD_EX32(info->idr[0], IDR0, ATS) < + FIELD_EX32(s->idr[0], IDR0, ATS)) { + error_setg(errp, "Host SMMUv3 doesn't support Address Translation = Services"); + return false; + } =20 /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D --=20 2.43.0 From nobody Mon Apr 6 16:48:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859816839158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 ATS support. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 4 +++- hw/arm/smmuv3.c | 17 ++++++++++++++--- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 4 +++- 4 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2bb142c47f..f21a6a9997 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -827,7 +827,9 @@ void smmuv3_accel_idr_override(SMMUv3State *s) s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + if (s->ats =3D=3D ON_OFF_AUTO_ON) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 068108e49b..a683402a0c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } =20 +bool smmuv3_ats_enabled(SMMUv3State *s) +{ + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -1966,12 +1971,17 @@ static bool smmu_validate_property(SMMUv3State *s, = Error **errp) } #endif =20 + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ats auto mode is not supported"); + return false; + } + if (!s->accel) { if (!s->ril) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } - if (s->ats) { + if (s->ats =3D=3D ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; @@ -2160,7 +2170,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Disable range invalidation support (for accel=3Don)"); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " - "platform has ATS support before enabling this"); + "platform has ATS support before enabling this. ats=3Dauto is not " + "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " "are 44 or 48 bits. Defaults to 44 bits"); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e..591cfc993c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..ce51a5b9b4 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,7 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; - bool ats; + OnOffAuto ats; uint8_t oas; uint8_t ssidsize; }; @@ -91,6 +91,8 @@ struct SMMUv3Class { ResettablePhases parent_phases; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=nathanc@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859891107158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 RIL property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 RIL support. Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL su= pport") Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 11 ++++++++--- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index f21a6a9997..c31b64295e 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* Only override RIL if user explicitly set OFF */ + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index a683402a0c..ea285bdf64 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1975,9 +1975,13 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ats auto mode is not supported"); return false; } + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ril auto mode is not supported"); + return false; + } =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2137,7 +2141,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), @@ -2167,7 +2171,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); object_class_property_set_description(klass, "ril", - "Disable range invalidation support (for accel=3Don)"); + "Disable range invalidation support (for accel=3Don). ril=3Dauto " + "is not supported."); object_class_property_set_description(klass, "ats", "Enable/disable ATS support (for accel=3Don). Please ensure host " "platform has ATS support before enabling this. ats=3Dauto is not " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ce51a5b9b4..c35e599bbc 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0 From nobody Mon Apr 6 16:48:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1773859853; cv=pass; d=zohomail.com; s=zohoarc; b=Qz8xqIwMf7BghB8Snm+E47mQqL97Up+7VCswxxVXK2it9cEuWF9Bo6msCyoMGhzecBxPprTzyW4ZpdpPJYCLByorvTuJGSGP6ikAfhkraNgZsD+X9uGkK/YuOYy+4nI4BQD/WGinYmtE4Co0DVn6hvpETJshkDxAumOTOEcQuLw= ARC-Message-Signature: i=2; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859855084158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce a new enum type property allowing to set a Substream ID size for HW-accelerated smmuv3. Values are auto and 0..20. The auto value allows SSID size property to be derived from host IOMMU capabilities. A value of 0 disables SubstreamID, while non-zero values specify the SSID size in bits. Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Tested-by: Shameer Kolothum --- hw/core/qdev-properties-system.c | 14 ++++++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 16 ++++++++++++++++ qapi/pragma.json | 1 + 4 files changed, 34 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index a402321f42..4aca1d4326 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -18,6 +18,7 @@ #include "qapi/qapi-types-block.h" #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-migration.h" +#include "qapi/qapi-types-misc-arm.h" #include "qapi/qapi-visit-virtio.h" #include "qapi/qmp/qerror.h" #include "qemu/ctype.h" @@ -723,6 +724,19 @@ const PropertyInfo qdev_prop_zero_page_detection =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- SsidSizeMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(SsidSizeMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_ssidsize_mode =3D { + .type =3D "SsidSizeMode", + .description =3D "ssidsize mode: auto, 0-20", + .enum_table =3D &SsidSizeMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index ec21732ce5..4708885164 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -14,6 +14,7 @@ extern const PropertyInfo qdev_prop_multifd_compression; extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; +extern const PropertyInfo qdev_prop_ssidsize_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -61,6 +62,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; #define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \ ZeroPageDetection) +#define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index f921d740f1..76ea0a09fa 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -45,3 +45,19 @@ # { "version": 3, "emulated": false, "kernel": true } = ] } ## { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] } + +## +# @SsidSizeMode: +# +# SMMUv3 SubstreamID size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# Values 0-20: SSIDSIZE value in bits. 0 disables SubstreamID. +# +# Since: 11.0 +## +{ 'enum': 'SsidSizeMode', + 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + '10', '11', '12', '13', '14', '15', '16', '17', '18', + '19', '20' ] } # order matters, see ssid_size_mode_auto() diff --git a/qapi/pragma.json b/qapi/pragma.json index 193bc39059..24aebbe8f5 100644 --- a/qapi/pragma.json +++ b/qapi/pragma.json @@ -68,6 +68,7 @@ 'S390CpuEntitlement', 'S390CpuPolarization', 'S390CpuState', + 'SsidSizeMode', 'String', 'StringWrapper', 'SysEmuTarget', --=20 2.43.0 From nobody Mon Apr 6 16:48:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859888138154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 SSIDSIZE value. Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configu= rable") Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++-- hw/arm/smmuv3.c | 19 ++++++++++--------- include/hw/arm/smmuv3-common.h | 1 - include/hw/arm/smmuv3.h | 3 ++- 4 files changed, 33 insertions(+), 13 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index c31b64295e..bc6cbfebc2 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) SMMUState *bs =3D opaque; SMMUv3State *s =3D ARM_SMMUV3(bs); =20 - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 +/* + * This returns the value of a SsidSizeMode value offset by 1 to + * account for the enum values offset by 1 from actual values. + * + * SSID_SIZE_MODE_0 =3D 1, SSID_SIZE_MODE_1 =3D 2, etc. so return 0 + * if SSID_SIZE_MODE_0 is passed as input, return 1 if + * SSID_SIZE_MODE_1 is passed as input, etc. + */ +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode) +{ + if (mode =3D=3D SSID_SIZE_MODE_AUTO) { + return 0; + } + return mode - 1; +} + void smmuv3_accel_idr_override(SMMUv3State *s) { if (!s->accel) { @@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser * has enabled it. */ - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + if (s->ssidsize > SSID_SIZE_MODE_0) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + ssidsize_mode_to_value(s->ssidsize)); + } } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index ea285bdf64..79018f8d66 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "hw/core/qdev-properties-system.h" #include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" @@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } =20 /* Multiple context descriptors require SubstreamID support */ - if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { + if (s->ssidsize =3D=3D SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require Substream= ID support. " "Configure ssidsize > 0 (requires accel=3Don)\n"); @@ -1979,6 +1980,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ril auto mode is not supported"); return false; } + if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + error_setg(errp, "ssidsize auto mode is not supported"); + return false; + } =20 if (!s->accel) { if (s->ril =3D=3D ON_OFF_AUTO_OFF) { @@ -1993,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } @@ -2011,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } - if (s->ssidsize > SMMU_SSID_MAX_BITS) { - error_setg(errp, "ssidsize must be in the range 0 to %d", - SMMU_SSID_MAX_BITS); - return false; - } =20 return true; } @@ -2144,7 +2144,8 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), - DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, + SSID_SIZE_MODE_0), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2185,7 +2186,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "Valid range is 0-20, where 0 disables SubstreamID support. " "Defaults to 0. A value greater than 0 is required to enable " - "PASID support."); + "PASID support. ssidsize=3Dauto is not supported."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 9f78bbe89e..7f0f992dfd 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -311,7 +311,6 @@ REG32(IDR1, 0x4) FIELD(IDR1, TABLES_PRESET, 30, 1) FIELD(IDR1, ECMDQ, 31, 1) =20 -#define SMMU_SSID_MAX_BITS 20 #define SMMU_IDR1_SIDSIZE 16 #define SMMU_CMDQS 19 #define SMMU_EVENTQS 19 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index c35e599bbc..ddf472493d 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -21,6 +21,7 @@ =20 #include "hw/arm/smmu-common.h" #include "qom/object.h" +#include "qapi/qapi-types-misc-arm.h" =20 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" =20 @@ -72,7 +73,7 @@ struct SMMUv3State { OnOffAuto ril; OnOffAuto ats; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859816838158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce a new enum type property allowing to set an Output Address Size. Values are auto, 32, 36, 40, 42, 44, 48, 52, and 56, where a value of N specifies an N-bit OAS. Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Tested-by: Shameer Kolothum --- hw/core/qdev-properties-system.c | 13 +++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 28 ++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index 4aca1d4326..a805ee2e1f 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- OasMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(OasMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_oas_mode =3D { + .type =3D "OasMode", + .description =3D "oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56", + .enum_table =3D &OasMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index 4708885164..2cbea16d61 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; extern const PropertyInfo qdev_prop_ssidsize_mode; +extern const PropertyInfo qdev_prop_oas_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; ZeroPageDetection) #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) +#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index 76ea0a09fa..5dbb4add91 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -61,3 +61,31 @@ 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '20' ] } # order matters, see ssid_size_mode_auto() + +## +# @OasMode: +# +# SMMUv3 Output Address Size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# @32: 32-bit output address size +# +# @36: 36-bit output address size +# +# @40: 40-bit output address size +# +# @42: 42-bit output address size +# +# @44: 44-bit output address size +# +# @48: 48-bit output address size +# +# @52: 52-bit output address size +# +# @56: 56-bit output address size +# +# Since: 11.0 +## +{ 'enum': 'OasMode', + 'data': [ 'auto', '32', '36', '40', '42', '44', '48', '52', '56' ] } --=20 2.43.0 From nobody Mon Apr 6 16:48:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859823529158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 OAS property from uint8_t to OasMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 OAS value. Fixes: a015ac990fd3 ("hw/arm/smmuv3-accel: Add property to specify OAS bits= ") Tested-by: Eric Auger Signed-off-by: Nathan Chen Acked-by: Markus Armbruster Reviewed-by: Eric Auger Reviewed-by: Shameer Kolothum Tested-by: Shameer Kolothum --- hw/arm/smmuv3-accel.c | 2 +- hw/arm/smmuv3.c | 16 ++++++++-------- include/hw/arm/smmuv3-common.h | 2 -- include/hw/arm/smmuv3.h | 2 +- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bc6cbfebc2..65c2f44880 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -850,7 +850,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s) } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas =3D=3D SMMU_OAS_48BIT) { + if (s->oas =3D=3D OAS_MODE_48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } =20 diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 79018f8d66..c67819d6f2 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1984,6 +1984,10 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "ssidsize auto mode is not supported"); return false; } + if (s->oas !=3D OAS_MODE_44 && s->oas !=3D OAS_MODE_48) { + error_setg(errp, "OAS can only be set to 44 or 48 bits"); + return false; + } =20 if (!s->accel) { if (s->ril =3D=3D ON_OFF_AUTO_OFF) { @@ -1994,7 +1998,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } - if (s->oas !=3D SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } @@ -2012,11 +2016,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); - return false; - } - return true; } =20 @@ -2143,7 +2142,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_44), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_0), }; @@ -2180,7 +2179,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "supported."); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits. Defaults to 44 bits. oas=3Dauto is not " + "supported."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-common.h index 7f0f992dfd..4609975edf 100644 --- a/include/hw/arm/smmuv3-common.h +++ b/include/hw/arm/smmuv3-common.h @@ -342,8 +342,6 @@ REG32(IDR5, 0x14) FIELD(IDR5, VAX, 10, 2); FIELD(IDR5, STALL_MAX, 16, 16); =20 -#define SMMU_OAS_44BIT 44 -#define SMMU_OAS_48BIT 48 #define SMMU_IDR5_OAS_44 4 #define SMMU_IDR5_OAS_48 5 =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ddf472493d..82f18eb090 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,7 +72,7 @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; =20 --=20 2.43.0 From nobody Mon Apr 6 16:48:29 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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From: Nathan Chen To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Eric Auger , Peter Maydell , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v4 8/8] qemu-options.hx: Document arm-smmuv3 device's accel properties Date: Wed, 18 Mar 2026 11:49:07 -0700 Message-ID: <20260318184907.4060030-9-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260318184907.4060030-1-nathanc@nvidia.com> References: <20260318184907.4060030-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR02CA0061.namprd02.prod.outlook.com (2603:10b6:a03:54::38) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|CH3PR12MB8233:EE_ X-MS-Office365-Filtering-Correlation-Id: 11f06742-96f3-4ec0-fa7c-08de851f1db6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773859848161154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Document arm-smmuv3 properties for setting HW-acceleration, Range Invalidation, and Address Translation Services support, as well as setting Output Address size and Substream ID size. Reviewed-by: Eric Auger Tested-by: Eric Auger Reviewed-by: Shameer Kolothum Signed-off-by: Nathan Chen Tested-by: Shameer Kolothum --- qemu-options.hx | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index 69e5a874c1..f8da35513a 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1279,13 +1279,43 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 -``-device arm-smmuv3,primary-bus=3Did`` +``-device arm-smmuv3,primary-bus=3Did[,option=3D...]`` This is only supported by ``-machine virt`` (ARM). =20 ``primary-bus=3Did`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. =20 + ``accel=3Don|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + The following options are available when accel=3Don. + Note: 'auto' mode is not currently supported. + + ``ril=3Don|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of iss= uing + separate commands to invalidate each page. Must match with host SM= MUv3 + Range Invalidation support. + + ``ats=3Don|off`` (default: off) + Support for Address Translation Services, which enables PCIe devic= es to + cache address translations in their local TLB and reduce latency. = Host + SMMUv3 must support ATS in order to enable this feature for the vI= OMMU. + + ``oas=3Dval`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be l= ess + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for st= age-2 + translation do not exceed the host's max supported IPA size. + + ``ssidsize=3Dval`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use c= ases + such as Shared Virtual Addressing (SVA) are supported. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0