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Iglesias" , qemu-arm@nongnu.org Subject: [PATCH-for-11.1 01/16] hw/riscv: Mark RISC-V specific peripherals as little-endian Date: Wed, 18 Mar 2026 11:31:06 +0100 Message-ID: <20260318103122.97244-2-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260318103122.97244-1-philmd@linaro.org> References: <20260318103122.97244-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1773829962693154100 These devices are only used by the RISC-V targets, which are only built as little-endian. Therefore the DEVICE_NATIVE_ENDIAN definition expand to DEVICE_LITTLE_ENDIAN (besides, the DEVICE_BIG_ENDIAN case isn't tested). Simplify directly using DEVICE_LITTLE_ENDIAN. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- hw/char/ibex_uart.c | 2 +- hw/char/shakti_uart.c | 2 +- hw/char/sifive_uart.c | 2 +- hw/misc/sifive_e_aon.c | 2 +- hw/misc/sifive_e_prci.c | 2 +- hw/misc/sifive_u_otp.c | 2 +- hw/misc/sifive_u_prci.c | 2 +- hw/riscv/riscv-iommu.c | 2 +- hw/sd/cadence_sdhci.c | 2 +- hw/timer/ibex_timer.c | 2 +- hw/timer/sifive_pwm.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index 127d219df3c..26ed1aea140 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -470,7 +470,7 @@ static void fifo_trigger_update(void *opaque) static const MemoryRegionOps ibex_uart_ops =3D { .read =3D ibex_uart_read, .write =3D ibex_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c index 2d1bc9cb8e2..d38920a03a0 100644 --- a/hw/char/shakti_uart.c +++ b/hw/char/shakti_uart.c @@ -103,7 +103,7 @@ static void shakti_uart_write(void *opaque, hwaddr addr, static const MemoryRegionOps shakti_uart_ops =3D { .read =3D shakti_uart_read, .write =3D shakti_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D {.min_access_size =3D 1, .max_access_size =3D 4}, .valid =3D {.min_access_size =3D 1, .max_access_size =3D 4}, }; diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index af17cf9a6ce..4e31842df5c 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -206,7 +206,7 @@ static void fifo_trigger_update(void *opaque) static const MemoryRegionOps sifive_uart_ops =3D { .read =3D sifive_uart_read, .write =3D sifive_uart_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c index e78f4f56725..ff2a7c18235 100644 --- a/hw/misc/sifive_e_aon.c +++ b/hw/misc/sifive_e_aon.c @@ -250,7 +250,7 @@ sifive_e_aon_write(void *opaque, hwaddr addr, static const MemoryRegionOps sifive_e_aon_ops =3D { .read =3D sifive_e_aon_read, .write =3D sifive_e_aon_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c index 400664aabae..a4a60e7b406 100644 --- a/hw/misc/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -75,7 +75,7 @@ static void sifive_e_prci_write(void *opaque, hwaddr addr, static const MemoryRegionOps sifive_e_prci_ops =3D { .read =3D sifive_e_prci_read, .write =3D sifive_e_prci_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 7205374bc39..cececd4f7a8 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -187,7 +187,7 @@ static void sifive_u_otp_write(void *opaque, hwaddr add= r, static const MemoryRegionOps sifive_u_otp_ops =3D { .read =3D sifive_u_otp_read, .write =3D sifive_u_otp_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/misc/sifive_u_prci.c b/hw/misc/sifive_u_prci.c index f51588623ab..4674d5925ea 100644 --- a/hw/misc/sifive_u_prci.c +++ b/hw/misc/sifive_u_prci.c @@ -112,7 +112,7 @@ static void sifive_u_prci_write(void *opaque, hwaddr ad= dr, static const MemoryRegionOps sifive_u_prci_ops =3D { .read =3D sifive_u_prci_read, .write =3D sifive_u_prci_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 98345b1280b..ef5d7df2385 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2375,7 +2375,7 @@ static MemTxResult riscv_iommu_mmio_read(void *opaque= , hwaddr addr, static const MemoryRegionOps riscv_iommu_mmio_ops =3D { .read_with_attrs =3D riscv_iommu_mmio_read, .write_with_attrs =3D riscv_iommu_mmio_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 8, diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index d576855a1a8..8476baf67fb 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -122,7 +122,7 @@ static void cadence_sdhci_write(void *opaque, hwaddr ad= dr, uint64_t val, static const MemoryRegionOps cadence_sdhci_ops =3D { .read =3D cadence_sdhci_read, .write =3D cadence_sdhci_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl =3D { .min_access_size =3D 4, .max_access_size =3D 4, diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index ee186521893..0f12531934d 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -234,7 +234,7 @@ static void ibex_timer_write(void *opaque, hwaddr addr, static const MemoryRegionOps ibex_timer_ops =3D { .read =3D ibex_timer_read, .write =3D ibex_timer_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, }; diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c index 780eaa50799..4f4f566cd4b 100644 --- a/hw/timer/sifive_pwm.c +++ b/hw/timer/sifive_pwm.c @@ -388,7 +388,7 @@ static void sifive_pwm_reset(DeviceState *dev) static const MemoryRegionOps sifive_pwm_ops =3D { .read =3D sifive_pwm_read, .write =3D sifive_pwm_write, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 static const VMStateDescription vmstate_sifive_pwm =3D { --=20 2.53.0