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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=nathanc@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773772782757154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Document arm-smmuv3 properties for setting HW-acceleration, Range Invalidation, and Address Translation Services support, as well as setting Output Address size and Substream ID size. Reviewed-by: Eric Auger Signed-off-by: Nathan Chen Reviewed-by: Shameer Kolothum --- qemu-options.hx | 35 ++++++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/qemu-options.hx b/qemu-options.hx index 69e5a874c1..0ba8322695 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1279,13 +1279,46 @@ SRST ``aw-bits=3Dval`` (val between 32 and 64, default depends on machine) This decides the address width of the IOVA address space. =20 -``-device arm-smmuv3,primary-bus=3Did`` +``-device arm-smmuv3,primary-bus=3Did[,option=3D...]`` This is only supported by ``-machine virt`` (ARM). =20 ``primary-bus=3Did`` Accepts either the default root complex (pcie.0) or a pxb-pcie based root complex. =20 + ``accel=3Don|off`` (default: off) + Enables guest to leverage host SMMUv3 features for acceleration. + Enabling accel configures the host SMMUv3 in nested mode to support + vfio-pci passthrough. + + ``ril=3Don|off`` (default: on) + Support for Range Invalidation, which allows the SMMUv3 driver to + invalidate TLB entries for a range of IOVAs at once instead of iss= uing + separate commands to invalidate each page. Must match with host SM= MUv3 + Range Invalidation support. Only applicable when accel=3Don. Setti= ng + 'auto' is currently not supported. + + ``ats=3Don|off`` (default: off) + Support for Address Translation Services, which enables PCIe devic= es to + cache address translations in their local TLB and reduce latency. = Host + SMMUv3 must support ATS in order to enable this feature for the vI= OMMU. + Only applicable when accel=3Don. Setting 'auto' is currently not + supported. + + ``oas=3Dval`` (supported values are 44 and 48. default: 44) + Sets the Output Address Size in bits. The value set here must be l= ess + than or equal to the host SMMUv3's supported OAS, so that the + intermediate physical addresses (IPA) consumed by host SMMU for st= age-2 + translation do not exceed the host's max supported IPA size. + Only applicable when accel=3Don. Setting 'auto' is currently not + supported. + + ``ssidsize=3Dval`` (val between 0 and 20. default: 0) + Sets the Substream ID size in bits. When set to a non-zero value, + PASID capability is advertised to the vIOMMU and accelerated use c= ases + such as Shared Virtual Addressing (SVA) are supported. Only applic= able + when accel=3Don. Setting 'auto' is currently not supported. + ``-device amd-iommu[,option=3D...]`` Enables emulation of an AMD-Vi I/O Memory Management Unit (IOMMU). Only available with ``-machine q35``, it supports the following option= s: --=20 2.43.0