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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=nathanc@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773772812344158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 SSIDSIZE property from uint8_t to SsidSizeMode. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of 'auto' value to match the host SMMUv3 SSIDSIZE value. Fixes: b8c6f8a69d27 ("hw/arm/smmuv3-accel: Make SubstreamID support configu= rable") Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 23 +++++++++++++++++++++-- hw/arm/smmuv3.c | 18 ++++++++++-------- include/hw/arm/smmuv3.h | 3 ++- 3 files changed, 33 insertions(+), 11 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index ddd927fa80..c90fa9f5bb 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -802,7 +802,7 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *opa= que) SMMUState *bs =3D opaque; SMMUv3State *s =3D ARM_SMMUV3(bs); =20 - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -817,6 +817,22 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 +/* + * This returns the value of a SsidSizeMode value offset by 1 to + * account for the enum values offset by 1 from actual values. + * + * SSID_SIZE_MODE_0 =3D 1, SSID_SIZE_MODE_1 =3D 2, etc. so return 0 + * if SSID_SIZE_MODE_0 is passed as input, return 1 if + * SSID_SIZE_MODE_1 is passed as input, etc. + */ +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode) +{ + if (mode =3D=3D SSID_SIZE_MODE_AUTO) { + return 0; + } + return mode - 1; +} + void smmuv3_accel_idr_override(SMMUv3State *s) { if (!s->accel) { @@ -842,7 +858,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser * has enabled it. */ - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + if (s->ssidsize > SSID_SIZE_MODE_0) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + ssidsize_mode_to_value(s->ssidsize)); + } } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 40d6aca83e..e7fec7a69e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "hw/core/qdev-properties-system.h" #include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" @@ -625,7 +626,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } =20 /* Multiple context descriptors require SubstreamID support */ - if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { + if (s->ssidsize =3D=3D SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require Substream= ID support. " "Configure ssidsize > 0 (requires accel=3Don)\n"); @@ -1984,7 +1985,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } @@ -2008,13 +2009,13 @@ static bool smmu_validate_property(SMMUv3State *s, = Error **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); + if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + error_setg(errp, "ssidsize cannot be set to auto"); return false; } - if (s->ssidsize > SMMU_SSID_MAX_BITS) { - error_setg(errp, "ssidsize must be in the range 0 to %d", - SMMU_SSID_MAX_BITS); + + if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { + error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } =20 @@ -2145,7 +2146,8 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), - DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, + SSID_SIZE_MODE_0), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index c35e599bbc..ddf472493d 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -21,6 +21,7 @@ =20 #include "hw/arm/smmu-common.h" #include "qom/object.h" +#include "qapi/qapi-types-misc-arm.h" =20 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" =20 @@ -72,7 +73,7 @@ struct SMMUv3State { OnOffAuto ril; OnOffAuto ats; uint8_t oas; - uint8_t ssidsize; + SsidSizeMode ssidsize; }; =20 typedef enum { --=20 2.43.0