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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c007::2; envelope-from=nathanc@nvidia.com; helo=MW6PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773772828242158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 RIL property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 RIL support. Fixes: bd715ff5bda9 ("hw/arm/smmuv3-accel: Add a property to specify RIL su= pport") Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 9 +++++++-- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 621ac531a5..ddd927fa80 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -823,8 +823,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* Only override RIL if user explicitly set OFF */ + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* Only override ATS if user explicitly set ON */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 3dead0bcd3..40d6aca83e 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1972,7 +1972,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) #endif =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2003,6 +2003,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ril cannot be set to auto"); + return false; + } + if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; @@ -2137,7 +2142,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_ON), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ce51a5b9b4..c35e599bbc 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0