From nobody Mon Apr 6 23:10:26 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1773772835; cv=pass; d=zohomail.com; s=zohoarc; b=ciBTlHlkTlWlaSAN4WhmbeF8uGcYiMDf2nv4bH4t4vKxbcjS0Y2Mc7q8pycIpfLLi/F+nqjInjYZE9An4YyRcJvwhR+BgH6a39ns7GZ7MF704bqj/fIPaNaBw9/nj6+FWkaWIMvbv91fM4CYd9nzZeRz9u8WdBcS+93rPlZeTP4= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773772835; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2AX029rXffkheo/ZA86aABv+cbWRlT02vFQMCkN5OMc=; b=iEIkKSo9zdCMwRDA6stlfuHDbO6yO4KtIYCIs7DKY8uBhLDYylf3a2lznL04GMsR57fOSDo+xgAVqF+BKueC1g77wtXnaVA11aI6pqDPCVQ3JfWa93XXjSg1V3iPU5gP/GsDJaZyFGYZf/OhnnjGJmDfNp/w7m923qhq0q5Ng8o= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773772835745111.98311970377517; Tue, 17 Mar 2026 11:40:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w2ZJh-00043C-55; Tue, 17 Mar 2026 14:38:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w2ZJf-00042N-VT; Tue, 17 Mar 2026 14:38:56 -0400 Received: from mail-eastusazlp170120007.outbound.protection.outlook.com ([2a01:111:f403:c101::7] helo=BL0PR03CU003.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w2ZJb-0002wk-2v; Tue, 17 Mar 2026 14:38:55 -0400 Received: from DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) by SN7PR12MB7452.namprd12.prod.outlook.com (2603:10b6:806:299::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9723.16; Tue, 17 Mar 2026 18:38:27 +0000 Received: from DS2PR12MB9567.namprd12.prod.outlook.com ([fe80::636:1b52:24ca:d7e5]) by DS2PR12MB9567.namprd12.prod.outlook.com ([fe80::636:1b52:24ca:d7e5%3]) with mapi id 15.20.9723.018; Tue, 17 Mar 2026 18:38:27 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ojVcLS4F+5ORympS9hsO0R9MQ20RAzqnyfIv+9iYDBqTfpR6AZAjCddFGoknIiZ6pitT68omxeVwaJawIOB0N2OwrSkBOZhWOIRo3S/K19OtzvHfK7qyLda6dJWabDX6I2JKWY0CkaM948DqcgYpBnaQGV5aulUW75JTEZ3w7249d8+besIUQPR11pYExW0B8COOX33tGNG00V3rykQiD5F6BjZN/eYFonHkRYLcKzFUVlxm/3rs9AnGkyVbEwcV2P6aYjJ4VZeypE2SbbyE5ppIQPAzVbXuiGfm379EX3FkzQ4YKU1CBT4dFLV1Qo+Y4U38s1kxiSB8UBabiJSkuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=2AX029rXffkheo/ZA86aABv+cbWRlT02vFQMCkN5OMc=; b=oklWNK46RYCYfYh5v2e9vH3gwws4qDia4DGtt710om90+v3odtIAMe7YMQZS92gV1BYl2Y2NmM45VgZi8r2n2m7Vw2ElSnjMDNendE/UA5kIQMmYUchO2lV52XHobeqBQ1g0S+nFeB68Z/bWORxKZzNwqngcpasvnFj41DVlD5ZsEFU/Un0wNopgAZrvZdUyHjAYSHAMFPyj54sANYwiRy/YEI4C01l70GQugdimq1l3QIl/N0LAKcq4If+ONnImhU8wWpBgTjgXYHx6YzBVechYthbB+KMajVhqcnVjJDC9rPsR2q889jb4PnqUOy0qPlYJINsSZv4vkk7QNucp0w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=2AX029rXffkheo/ZA86aABv+cbWRlT02vFQMCkN5OMc=; b=FzEB20iiTIwurzVdFAggWdVoq8yjKzVVBCLtnIArZJxcvjvkjhPVQ5ql4kTOmgcIC/XrVcs6N/I/g3i+X2prVkNzUUOBMmCuTLDgujgkLQHppOmRsmQNCOtwfGLxMixV6yORWag8rX+kZP3m4b3xTcHHab5qVRiMg7mZlIn2CapiwdWlB7gIpvLmF8s94oTk+JWR8/+D6x+aXSmWPg1pCyFVtqK9W7DioP8v5iS/Mgy1VaDFDSt1AiHLO4x6GoT/kXM0r0BD/hHvArdd74Am+Zvy8u79X241eM5NvrlLeya++o6QkHO5XCtOoGimtQYgHxvW4Ykz41S7G9RfocmQNg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; From: Nathan Chen To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Cc: Eric Auger , Peter Maydell , Shannon Zhao , "Michael S . Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eric Blake , Markus Armbruster , Shameer Kolothum , Matt Ochs , Nicolin Chen , Nathan Chen Subject: [PATCH v3 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto Date: Tue, 17 Mar 2026 11:37:49 -0700 Message-ID: <20260317183755.3721625-3-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317183755.3721625-1-nathanc@nvidia.com> References: <20260317183755.3721625-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR08CA0056.namprd08.prod.outlook.com (2603:10b6:a03:117::33) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|SN7PR12MB7452:EE_ X-MS-Office365-Filtering-Correlation-Id: a6aca428-7488-424f-13d1-08de84546103 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|366016|1800799024|376014|7416014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: 5minKwOv6MIOvN+oeJq/bcciwOwxbZrcTy4GbtrD9a1yNMzveMx1WodwrnJ79NYMbx0YwMBx7JeTV9mDLofhOMWwjr40BaT1JSmO188fikQ5fo/jBQDjQ5/vxra8KvX79sulcTmQUn4RW6qymL25ddNcwjdrb+obpepLl/gjCdh609PdGO8CSTyG1BT6IaQ8Ek9+pFcGtkom2VsJNv5iedBQjH/G3dPgwiUvar7qChvSC58YWlHVPdkkB2P+WW2S9l9oM6Cw1npHf/DQzUgpUblIfIcPMMEbkIwI4cRmmYq4G8VdN+gjLYSWBkzrCNf5z6mjbQJ4KSyct7yK7ASK1ejwUSQf1MEMi8/hHscrCLQQBgRHazSOuX4rPZ/cjG4GYoQGFnBRXN1cdygnrlk6GBwNkfibgEphna57zUxG1v+kIWzrlCymc+fOMwaMbS/cwCiQYyBQfL+TkLsq188W7xPM0oPNeUvNRV+iBG4QeWmk/Dwvv7CclcCY0LOUdmldFdWpDnCVtIMffONldvFB01QnuDYsxLJjfWql0lv6pP06IdjN9v4qmhj6aCKu6DKKHeEmPAgrlO1mizv+6Qno1UjQpIqFIrvQ3k77fUc8BimTlsT2oZkmpP0zZVqFmxxSW2mG/GNPEDxvVjwM69RNGIrvx1thiHaaJMnIQZStrVkfgZKxNgwSj/uHvroz1EEiGGLy1asOGdlAlCla04ophUFvkUUOb6ctJNj3+edQhME= X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DS2PR12MB9567.namprd12.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230040)(366016)(1800799024)(376014)(7416014)(18002099003)(56012099003)(22082099003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?rGkmqnHMmmmNWSbjry8LCF+rdc6oDsRxoAVo8mZWNPQGw4+Rvdy5BKKA61EI?= =?us-ascii?Q?tGNcwyCuTxRIpazzZZJNkrWXNcoap0MikscAUhcEwe05OHHVXoAmYXpeiSnx?= =?us-ascii?Q?vxM893Z38SxMYpinPTOtVWo2Blwqk3iKNY2tY/6UNguf09DyQ28dmJy00qdW?= =?us-ascii?Q?fvgPCIC2WrSuRtr179XUQtZtRPBPbTHNDgHDUohRnj48gZMk+68Ck5Fn1NNG?= =?us-ascii?Q?rbZZjBcD7eFUtttfzTosPM7bAUBvx7sR77h+MNNKpAVYatOzozJZKa49wNZG?= =?us-ascii?Q?tnle0UrRDA3sHrosUoopFROl/MRzNuicod41XtR5RP3/hOLwtAz7d9TKytkp?= =?us-ascii?Q?sayxkH+B/yUtTjeUSZZG6/ngso+FAzXsEldazbcNwzfAGozrPsW2rflMiQDK?= =?us-ascii?Q?TPw6ScpOKxfXYc+0Gkunz9qKTzP17MnWxmTi5UQ6lWXYv/TD/uFEgubBahDd?= =?us-ascii?Q?peRPdaOfXxnqne0CCBhM3HDaTis468CgfHpxUUd3w4BMCIl3MfWCO/LdN+vk?= =?us-ascii?Q?NAAwmycHNxAZ94Jkrn0/t2Km2gD2XKdz2ZVaDzT9c8yv1YM8L3+dkAMZX1l9?= =?us-ascii?Q?dAMEwEkEje9Fa4yleiTs1VQ6IaSg6eOXf94TBvtufINC7XrlItqsKd3eZx2h?= =?us-ascii?Q?OpMHePITNHZvIdePiWFneLDeh3hwzTcrVKh7kFaUBXYhxTakWfe9PDm1xajI?= =?us-ascii?Q?hw/Fhu0SAe250yV6k0ETtQVuypUJWy6glnuuvVxR3IqzaJ7qQ4YGwjlFjJtI?= =?us-ascii?Q?kFC9BMEwctmyd2QZuHd/LXzNoKspj32OzQTXPqvmQ0Q4E1xYU4tz1sgcw1CU?= =?us-ascii?Q?9DeOjhGVY0LQ7zzVNHX/sXJxJWRkYUFGKGwQsAEpsNGriyE4cgbZTMpl/U6j?= =?us-ascii?Q?AnTmBDmaOaffBPbVHv7wWx5u7f42F8oqwOhazgDNZQKScFAu9r22TVczKRmu?= =?us-ascii?Q?HBlWs+ZG/C/mVukSzu46fV7FoYL/PrORB4DSPG61DbMJXO7JsIiXylk78Y/w?= =?us-ascii?Q?TliDClwcH8z9Wi136aKdKF8x108r+mjPIQzRdEvvF/dXfOMBwQMusYBMQA8u?= =?us-ascii?Q?4VXrZHp0O/CBMDOd9z5yI0ZYvOYPYMH/yZ6jItXyoDzU9tMxjozUm7Pi6YpK?= =?us-ascii?Q?UreVN+C4Z1C8rVnJvApkb2OCAa/MuN9ouBQGRxaotBDkCB23cE/bVinwzqCN?= =?us-ascii?Q?BcleVMzKcIsgnFJBfDdPxCespoRYnD9pZN82BB0GT3F8SjRMBWqfi41Y/noX?= =?us-ascii?Q?TEGVBQW0e3JDsxY6toBJ79TYT1kxlqPdj9TbrYqGgUt+Fre0ee8a6ySdke4K?= =?us-ascii?Q?G1G2CVrwU7zVMsJUZajgBL7R6QLsaZQNjrS3g5LSeiF5LsuO4Z+/POUe9uAF?= =?us-ascii?Q?GeVj7kJOhHS5vkNCItZvZgehhOr3nvRdk98kB+dF8JwPCjPWhRdy2o+DPIwC?= =?us-ascii?Q?2ywfAxp2vn+/hN7ejMZ8/fhFylVkX8iVA7V/mqxleeRQ4+aAyVTzWqDzOy1F?= =?us-ascii?Q?FmE4PwA8vcxYm5+C0bLmOsB5rH2vRgy7My7a/cIVNqG1AeQ5jauDbM1OXpzu?= =?us-ascii?Q?xg2yKKI+ZQJ72M73njbt2i67YCDEvdtdlc3Js9wb2Wfv4XE/TzUXLSaXSrN0?= =?us-ascii?Q?61IJBP/Fzibo+59IYEa5tkUp6s7NAW9JCNZESIQE2IYOZXIC/kl1UuWK2jfO?= =?us-ascii?Q?y865HeBR9oWzbKO2omTSbaq+ggyZv0W8tXLnudeastjJQy0l4XAHIMqKnPiL?= =?us-ascii?Q?XVBUlBbaaA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: a6aca428-7488-424f-13d1-08de84546103 X-MS-Exchange-CrossTenant-AuthSource: DS2PR12MB9567.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2026 18:38:27.4117 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: LG3xlE92mI2jLq7AW4zfhz+SUaOh+nmRn/W7CYPyrYih/uNkGBO+DHsIzs4Oc89c9KefWzgdk8f0TM0LQdJ/Wg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7452 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c101::7; envelope-from=nathanc@nvidia.com; helo=BL0PR03CU003.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773772836314158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 ATS property from bool to OnOffAuto. The 'auto' value is not implemented, as this commit is meant to set the property to the correct type and avoid breaking JSON/QMP when the auto mode is introduced. A future patch will implement resolution of the 'auto' value to match the host SMMUv3 ATS support. Fixes: f7f5013a55a3 ("hw/arm/smmuv3-accel: Add support for ATS") Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 6 ++++-- hw/arm/smmuv3.c | 14 ++++++++++++-- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 4 +++- 4 files changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 2bb142c47f..621ac531a5 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -826,8 +826,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); =20 - /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + /* Only override ATS if user explicitly set ON */ + if (s->ats =3D=3D ON_OFF_AUTO_ON) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 068108e49b..3dead0bcd3 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } =20 +bool smmuv3_ats_enabled(SMMUv3State *s) +{ + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -1971,7 +1976,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } - if (s->ats) { + if (s->ats =3D=3D ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } @@ -1993,6 +1998,11 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) return false; } =20 + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + error_setg(errp, "ats cannot be set to auto"); + return false; + } + if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; @@ -2128,7 +2138,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e..591cfc993c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..ce51a5b9b4 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,7 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; - bool ats; + OnOffAuto ats; uint8_t oas; uint8_t ssidsize; }; @@ -91,6 +91,8 @@ struct SMMUv3Class { ResettablePhases parent_phases; }; =20 +bool smmuv3_ats_enabled(struct SMMUv3State *s); + #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 --=20 2.43.0