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Tue, 17 Mar 2026 10:50:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH 2/3] target/mips: Free mvp in unrealize Date: Tue, 17 Mar 2026 17:50:29 +0000 Message-ID: <20260317175031.3035740-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260317175031.3035740-1-peter.maydell@linaro.org> References: <20260317175031.3035740-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1773769880995158500 Content-Type: text/plain; charset="utf-8" We allocate memory for cpu->mvp in mips_cpu_realizefn(), but we never free it, which causes memory leaks like this: Direct leak of 24 byte(s) in 2 object(s) allocated from: #0 0x5f9458e61c8d in calloc (/home/pm215/qemu/build/san/qemu-mips+0= x4d8c8d) (BuildId: 4153e33b3d08657a71ce2a04a82d0c2954966d9c) #1 0x74761891a771 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.s= o.0+0x63771) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x5f94590687aa in mvp_init /home/pm215/qemu/build/san/../../targ= et/mips/cpu-defs.c.inc:1037:16 #3 0x5f94590687aa in mips_cpu_realizefn /home/pm215/qemu/build/san/= ../../target/mips/cpu.c:489:5 #4 0x5f9459366a3a in device_set_realized /home/pm215/qemu/build/san= /../../hw/core/qdev.c:523:13 #5 0x5f9459380a49 in property_set_bool /home/pm215/qemu/build/san/.= ./../qom/object.c:2376:5 #6 0x5f945937bace in object_property_set /home/pm215/qemu/build/san= /../../qom/object.c:1450:5 #7 0x5f945938816c in object_property_set_qobject /home/pm215/qemu/b= uild/san/../../qom/qom-qobject.c:28:10 #8 0x5f94592cc100 in cpu_copy /home/pm215/qemu/build/san/../../linu= x-user/main.c:240:25 #9 0x5f9459309931 in do_syscall1 /home/pm215/qemu/build/san/../../l= inux-user/syscall.c #10 0x5f94593058d8 in do_syscall /home/pm215/qemu/build/san/../../l= inux-user/syscall.c:14422:15 #11 0x5f945905c73e in cpu_loop /home/pm215/qemu/build/san/../../lin= ux-user/mips/cpu_loop.c:124:23 for linux-user, where each new guest thread is a new CPU object that we need to destroy on thread exit. Add an unrealize method which frees this memory. Signed-off-by: Peter Maydell --- target/mips/cpu.c | 12 ++++++++++++ target/mips/cpu.h | 1 + 2 files changed, 13 insertions(+) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 789ca188b5..0663cda003 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -502,6 +502,16 @@ static void mips_cpu_realizefn(DeviceState *dev, Error= **errp) mcc->parent_realize(dev, errp); } =20 +static void mips_cpu_unrealizefn(DeviceState *dev) +{ + MIPSCPU *cpu =3D MIPS_CPU(dev); + MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(dev); + + g_free(cpu->mvp); + + mcc->parent_unrealize(dev); +} + static void mips_cpu_initfn(Object *obj) { MIPSCPU *cpu =3D MIPS_CPU(obj); @@ -606,6 +616,8 @@ static void mips_cpu_class_init(ObjectClass *c, const v= oid *data) device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); + device_class_set_parent_unrealize(dc, mips_cpu_unrealizefn, + &mcc->parent_unrealize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, &mcc->parent_phases); =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 8de3178b6d..ca36ca0d6f 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1225,6 +1225,7 @@ struct MIPSCPUClass { CPUClass parent_class; =20 DeviceRealize parent_realize; + DeviceUnrealize parent_unrealize; ResettablePhases parent_phases; const struct mips_def_t *cpu_def; =20 --=20 2.43.0