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mx.zohomail.com; dkim=pass header.i=linux.beauty; spf=pass smtp.mailfrom=me@linux.beauty; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1773718405; s=zmail; d=linux.beauty; i=me@linux.beauty; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=o/k9W/3pb0zb4BQ0MZjpr4wFcJrIko/dda2WW35D1BM=; b=B0HHyLS5yJA7J5vBY5BZx7TUOGyoZO9L2lW4mITZKPLYFdaB114qqKB9rI1RXAwR bMEwzPX7J8zbO76m6Vy8qho3sMxWA4ibfG1TN7ZhNoei3/A9RN1mOMp2BieROpnPxxR fz/HKDfz+wBF5QAVa0WLRqnAlMuHsznfkRLNcB3A= From: Li Chen To: Jonathan Cameron , Fan Ni Cc: qemu-devel@nongnu.org, Li Chen Subject: [PATCH 3/3] cxl: update fixed window mappings on decoder programming Date: Tue, 17 Mar 2026 11:33:03 +0800 Message-ID: <20260317033304.3185291-4-me@linux.beauty> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260317033304.3185291-1-me@linux.beauty> References: <20260317033304.3185291-1-me@linux.beauty> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Invoke cxl_fmws_update_mappings() when HDM decoder registers are updated on host components and Type-3 devices, so fixed memory windows can switch between the MMIO dispatcher and the RAM alias overlay as the guest commits/uncommits decoder state. Signed-off-by: Li Chen --- hw/cxl/cxl-component-utils.c | 2 ++ hw/mem/cxl_type3.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index 07aabe331c..8a36a62db0 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -12,6 +12,7 @@ #include "qapi/error.h" #include "hw/pci/pci.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" =20 /* CXL r3.1 Section 8.2.4.20.1 CXL HDM Decoder Capability Register */ int cxl_decoder_count_enc(int count) @@ -209,6 +210,7 @@ static void cxl_cache_mem_write_reg(void *opaque, hwadd= r offset, uint64_t value, if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { dumb_hdm_handler(cxl_cstate, offset, value); + cxl_fmws_update_mappings(); } else if (offset =3D=3D A_CXL_BI_RT_CTRL || offset =3D=3D A_CXL_BI_DECODER_CTRL) { bi_handler(cxl_cstate, offset, value); diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index bf79db6082..8ad36e6f53 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -29,6 +29,7 @@ #include "system/hostmem.h" #include "system/numa.h" #include "hw/cxl/cxl.h" +#include "hw/cxl/cxl_host.h" #include "hw/pci/msix.h" =20 /* type3 device private */ @@ -628,6 +629,11 @@ static void ct3d_reg_write(void *opaque, hwaddr offset= , uint64_t value, } else if (should_uncommit) { hdm_decoder_uncommit(ct3d, which_hdm); } + + if (offset >=3D A_CXL_HDM_DECODER_CAPABILITY && + offset <=3D A_CXL_HDM_DECODER3_TARGET_LIST_HI) { + cxl_fmws_update_mappings(); + } } =20 /* @@ -1377,6 +1383,7 @@ static void ct3d_reset(DeviceState *dev) cxl_component_register_init_common(reg_state, write_msk, CXL2_TYPE3_DEVICE, ct3d->hdmdb); cxl_device_register_init_t3(ct3d, CXL_T3_MSIX_MBOX); + cxl_fmws_update_mappings(); =20 /* * Bring up an endpoint to target with MCTP over VDM. --=20 2.52.0