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Thu, 12 Mar 2026 23:24:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier , Paolo Bonzini , Thomas Huth , Anton Johansson Subject: [PATCH v2 30/38] hw/riscv: Include full path to target 'cpu.h' header Date: Fri, 13 Mar 2026 07:20:46 +0100 Message-ID: <20260313062055.2188-31-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260313062055.2188-1-philmd@linaro.org> References: <20260313062055.2188-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1773383083842158500 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier --- hw/misc/riscv_cmgcr.c | 2 +- hw/misc/riscv_cpc.c | 2 +- hw/riscv/microblaze-v-generic.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/misc/riscv_cmgcr.c b/hw/misc/riscv_cmgcr.c index a4d56e3b308..0390996f78b 100644 --- a/hw/misc/riscv_cmgcr.c +++ b/hw/misc/riscv_cmgcr.c @@ -21,7 +21,7 @@ #include "hw/core/qdev-properties.h" #include "exec/target_page.h" =20 -#include "cpu.h" +#include "target/riscv/cpu.h" =20 #define CM_RESET_VEC 0x1FC00000 #define GCR_ADDRSPACE_SZ 0x8000 diff --git a/hw/misc/riscv_cpc.c b/hw/misc/riscv_cpc.c index e04ccdf54fa..37fdd0b39ba 100644 --- a/hw/misc/riscv_cpc.c +++ b/hw/misc/riscv_cpc.c @@ -13,7 +13,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" +#include "target/riscv/cpu.h" #include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generi= c.c index d56b64792d7..b0494b1ac50 100644 --- a/hw/riscv/microblaze-v-generic.c +++ b/hw/riscv/microblaze-v-generic.c @@ -16,7 +16,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" +#include "target/riscv/cpu.h" #include "hw/core/sysbus.h" #include "system/system.h" #include "net/net.h" --=20 2.53.0