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Thu, 12 Mar 2026 19:19:03 -0700 (PDT) From: Lucas Amaral To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, agraf@csgraf.de, Lucas Amaral Subject: [PATCH v2 3/3] target/arm: wire ISV=0 emulation into HVF and WHPX Date: Thu, 12 Mar 2026 23:18:50 -0300 Message-ID: <20260313021850.42379-4-lucaaamaral@gmail.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260313021850.42379-1-lucaaamaral@gmail.com> References: <20260309214852.92545-1-lucaaamaral@gmail.com> <20260313021850.42379-1-lucaaamaral@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1330; envelope-from=lucaaamaral@gmail.com; helo=mail-dy1-x1330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_BARE_IP_2=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773368392283154100 Content-Type: text/plain; charset="utf-8" Connect the ISV=3D0 emulation library to the HVF and WHPX backends. Each implements arm_emul_ops callbacks over CPUARMState and cpu_memory_rw_debug(). Replaces the assert(isv) with instruction fetch, decode, and emulation via arm_emul_insn(). Signed-off-by: Lucas Amaral --- target/arm/hvf/hvf.c | 94 ++++++++++++++++++++++++++++++++++++-- target/arm/whpx/whpx-all.c | 86 +++++++++++++++++++++++++++++++++- 2 files changed, 176 insertions(+), 4 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d79469c..2a57b97 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -30,6 +30,7 @@ #include "qemu/main-loop.h" #include "system/cpus.h" #include "arm-powerctl.h" +#include "emulate/arm_emulate.h" #include "target/arm/cpu.h" #include "target/arm/internals.h" #include "target/arm/multiprocessing.h" @@ -797,6 +798,59 @@ static uint64_t hvf_get_reg(CPUState *cpu, int rt) return val; } =20 +/* + * arm_emul_ops callbacks for HVF + * + * State must already be synchronized (cpu_synchronize_state) before + * calling arm_emul_insn(). Reads/writes env->xregs[] directly to + * correctly handle register 31 as SP and avoid redundant HVF API calls. + */ + +static uint64_t hvf_emul_read_gpr(CPUState *cpu, int reg) +{ + return ARM_CPU(cpu)->env.xregs[reg]; +} + +static void hvf_emul_write_gpr(CPUState *cpu, int reg, uint64_t val) +{ + ARM_CPU(cpu)->env.xregs[reg] =3D val; + cpu->vcpu_dirty =3D true; +} + +static void hvf_emul_read_fpreg(CPUState *cpu, int reg, void *buf, int siz= e) +{ + memcpy(buf, &ARM_CPU(cpu)->env.vfp.zregs[reg], size); +} + +static void hvf_emul_write_fpreg(CPUState *cpu, int reg, + const void *buf, int size) +{ + CPUARMState *env =3D &ARM_CPU(cpu)->env; + memset(&env->vfp.zregs[reg], 0, sizeof(env->vfp.zregs[reg])); + memcpy(&env->vfp.zregs[reg], buf, size); + cpu->vcpu_dirty =3D true; +} + +static int hvf_emul_read_mem(CPUState *cpu, uint64_t va, void *buf, int si= ze) +{ + return cpu_memory_rw_debug(cpu, va, buf, size, false); +} + +static int hvf_emul_write_mem(CPUState *cpu, uint64_t va, + const void *buf, int size) +{ + return cpu_memory_rw_debug(cpu, va, (void *)buf, size, true); +} + +static const struct arm_emul_ops hvf_arm_emul_ops =3D { + .read_gpr =3D hvf_emul_read_gpr, + .write_gpr =3D hvf_emul_write_gpr, + .read_fpreg =3D hvf_emul_read_fpreg, + .write_fpreg =3D hvf_emul_write_fpreg, + .read_mem =3D hvf_emul_read_mem, + .write_mem =3D hvf_emul_write_mem, +}; + static void clamp_id_aa64mmfr0_parange_to_ipa_size(ARMISARegisters *isar) { uint32_t ipa_size =3D chosen_ipa_bit_size ? @@ -1871,10 +1925,44 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) assert(!s1ptw); =20 /* - * TODO: ISV will be 0 for SIMD or SVE accesses. - * Inject the exception into the guest. + * ISV=3D0: syndrome doesn't carry access size/register info. + * Fetch and emulate via target/arm/emulate/. + * Unhandled instructions log an error and advance PC. */ - assert(isv); + if (!isv) { + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + uint32_t insn; + ArmEmulResult r; + + cpu_synchronize_state(cpu); + + if (cpu_memory_rw_debug(cpu, env->pc, + (uint8_t *)&insn, 4, false) !=3D 0) { + error_report("HVF: cannot read insn at pc=3D0x%" PRIx64, + (uint64_t)env->pc); + advance_pc =3D true; + break; + } + + r =3D arm_emul_insn(cpu, &hvf_arm_emul_ops, insn); + if (r =3D=3D ARM_EMUL_UNHANDLED) { + /* + * TODO: Inject data abort into guest instead of + * advancing PC. Requires setting ESR_EL1/FAR_EL1/ + * ELR_EL1/SPSR_EL1 and redirecting to VBAR_EL1. + */ + error_report("HVF: ISV=3D0 unhandled insn 0x%08x at " + "pc=3D0x%" PRIx64, insn, (uint64_t)env->pc); + } else if (r =3D=3D ARM_EMUL_ERR_MEM) { + error_report("HVF: ISV=3D0 memory error emulating " + "insn 0x%08x at pc=3D0x%" PRIx64, + insn, (uint64_t)env->pc); + } + + advance_pc =3D true; + break; + } =20 /* * Emulate MMIO. diff --git a/target/arm/whpx/whpx-all.c b/target/arm/whpx/whpx-all.c index 40ada2d..c57abef 100644 --- a/target/arm/whpx/whpx-all.c +++ b/target/arm/whpx/whpx-all.c @@ -37,6 +37,7 @@ #include "whpx_arm.h" #include "hw/arm/bsa.h" #include "arm-powerctl.h" +#include "emulate/arm_emulate.h" =20 #include #include @@ -377,6 +378,53 @@ static void whpx_set_gp_reg(CPUState *cpu, int rt, uin= t64_t val) whpx_set_reg(cpu, reg, reg_val); } =20 +/* arm_emul_ops callbacks for WHPX */ + +static uint64_t whpx_emul_read_gpr(CPUState *cpu, int reg) +{ + return ARM_CPU(cpu)->env.xregs[reg]; +} + +static void whpx_emul_write_gpr(CPUState *cpu, int reg, uint64_t val) +{ + ARM_CPU(cpu)->env.xregs[reg] =3D val; + cpu->vcpu_dirty =3D true; +} + +static void whpx_emul_read_fpreg(CPUState *cpu, int reg, void *buf, int si= ze) +{ + memcpy(buf, &ARM_CPU(cpu)->env.vfp.zregs[reg], size); +} + +static void whpx_emul_write_fpreg(CPUState *cpu, int reg, + const void *buf, int size) +{ + CPUARMState *env =3D &ARM_CPU(cpu)->env; + memset(&env->vfp.zregs[reg], 0, sizeof(env->vfp.zregs[reg])); + memcpy(&env->vfp.zregs[reg], buf, size); + cpu->vcpu_dirty =3D true; +} + +static int whpx_emul_read_mem(CPUState *cpu, uint64_t va, void *buf, int s= ize) +{ + return cpu_memory_rw_debug(cpu, va, buf, size, false); +} + +static int whpx_emul_write_mem(CPUState *cpu, uint64_t va, + const void *buf, int size) +{ + return cpu_memory_rw_debug(cpu, va, (void *)buf, size, true); +} + +static const struct arm_emul_ops whpx_arm_emul_ops =3D { + .read_gpr =3D whpx_emul_read_gpr, + .write_gpr =3D whpx_emul_write_gpr, + .read_fpreg =3D whpx_emul_read_fpreg, + .write_fpreg =3D whpx_emul_write_fpreg, + .read_mem =3D whpx_emul_read_mem, + .write_mem =3D whpx_emul_write_mem, +}; + static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_ACCESS_CONTEXT *ctx) { uint64_t syndrome =3D ctx->Syndrome; @@ -391,7 +439,43 @@ static int whpx_handle_mmio(CPUState *cpu, WHV_MEMORY_= ACCESS_CONTEXT *ctx) uint64_t val =3D 0; =20 assert(!cm); - assert(isv); + + /* + * ISV=3D0: syndrome doesn't carry access size/register info. + * Fetch and decode the faulting instruction via the emulation library. + */ + if (!isv) { + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + uint32_t insn; + ArmEmulResult r; + + cpu_synchronize_state(cpu); + + if (cpu_memory_rw_debug(cpu, env->pc, + (uint8_t *)&insn, 4, false) !=3D 0) { + error_report("WHPX: cannot read insn at pc=3D0x%" PRIx64, + (uint64_t)env->pc); + return 0; + } + + r =3D arm_emul_insn(cpu, &whpx_arm_emul_ops, insn); + if (r =3D=3D ARM_EMUL_UNHANDLED) { + /* + * TODO: Inject data abort into guest instead of + * advancing PC. Requires setting ESR_EL1/FAR_EL1/ + * ELR_EL1/SPSR_EL1 and redirecting to VBAR_EL1. + */ + error_report("WHPX: ISV=3D0 unhandled insn 0x%08x at " + "pc=3D0x%" PRIx64, insn, (uint64_t)env->pc); + } else if (r =3D=3D ARM_EMUL_ERR_MEM) { + error_report("WHPX: ISV=3D0 memory error emulating " + "insn 0x%08x at pc=3D0x%" PRIx64, + insn, (uint64_t)env->pc); + } + + return 0; + } =20 if (iswrite) { val =3D whpx_get_gp_reg(cpu, srt); --=20 2.52.0