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Tsirkin" , Igor Mammedov , Ani Sinha , Shannon Zhao , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Eduardo Habkost , Eric Blake , Markus Armbruster , Shameer Kolothum , Nicolin Chen , Matt Ochs , Nathan Chen Subject: [PATCH v2 2/8] hw/arm/smmuv3-accel: Change ATS property to OnOffAuto Date: Thu, 12 Mar 2026 14:03:21 -0700 Message-ID: <20260312210328.2016191-3-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260312210328.2016191-1-nathanc@nvidia.com> References: <20260312210328.2016191-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR03CA0036.namprd03.prod.outlook.com (2603:10b6:a03:33e::11) To DS2PR12MB9567.namprd12.prod.outlook.com (2603:10b6:8:27c::8) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PR12MB9567:EE_|EAYPR12MB999156:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e136733-86ef-4ab3-d38a-08de807adbb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c10c::1; envelope-from=nathanc@nvidia.com; helo=SA9PR02CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773349507544154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Change accel SMMUv3 ATS property from bool to OnOffAuto. Setting 'auto' will result in the default value being used, i.e. 0 in IDR0 which translates to 'off'. A future patch will implement resolution of 'auto' value to match the host SMMUv3 ATS support. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 8 ++++++-- hw/arm/smmuv3.c | 9 +++++++-- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 4 +++- 4 files changed, 17 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index fe78ce69a5..5d14abe307 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -827,8 +827,12 @@ void smmuv3_accel_idr_override(SMMUv3State *s) /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); =20 - /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + /* Only override ATS if user explicitly set ON or OFF */ + if (s->ats =3D=3D ON_OFF_AUTO_ON) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } else if (s->ats =3D=3D ON_OFF_AUTO_OFF) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 0); + } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 068108e49b..862ca945d5 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -317,6 +317,11 @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } =20 +bool smmuv3_ats_enabled(SMMUv3State *s) +{ + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -1971,7 +1976,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } - if (s->ats) { + if (s->ats =3D=3D ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } @@ -2128,7 +2133,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_OFF), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e..591cfc993c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.ats =3D smmuv3_ats_enabled(ARM_SMMUV3(obj)); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..ce51a5b9b4 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,7 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; bool ril; - bool ats; + OnOffAuto ats; uint8_t oas; uint8_t ssidsize; }; @@ -91,6 +91,8 @@ struct SMMUv3Class { ResettablePhases parent_phases; }; =20 +bool smmuv3_ats_enabled(struct SMMUv3State *s); + #define TYPE_ARM_SMMUV3 "arm-smmuv3" OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) =20 --=20 2.43.0