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Thu, 12 Mar 2026 06:42:17 -0700 (PDT) From: James Wainwright To: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, alistair.francis@wdc.com, Emmanuel Blot , James Wainwright Subject: [PATCH v4 3/3] disas: diassemble RISC-V xlrbr (crc32) instructions Date: Thu, 12 Mar 2026 13:42:09 +0000 Message-ID: <20260312134210.5823-4-james.wainwright@lowrisc.org> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20260312134210.5823-1-james.wainwright@lowrisc.org> References: <20260312134210.5823-1-james.wainwright@lowrisc.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=james.wainwright@lowrisc.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @lowrisc.org) X-ZM-MESSAGEID: 1773323015152158501 Content-Type: text/plain; charset="utf-8" From: Emmanuel Blot Placed in a separate file as a vendor extension. Signed-off-by: James Wainwright Reviewed-by: Alistair Francis --- MAINTAINERS | 2 +- disas/meson.build | 3 +- disas/riscv-xlrbr.c | 79 +++++++++++++++++++++++++++++++++++++++++++++ disas/riscv-xlrbr.h | 19 +++++++++++ disas/riscv.c | 2 ++ 5 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 disas/riscv-xlrbr.c create mode 100644 disas/riscv-xlrbr.h diff --git a/MAINTAINERS b/MAINTAINERS index 847fd414bc..12f106f4c4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4154,7 +4154,7 @@ M: Alistair Francis L: qemu-riscv@nongnu.org S: Maintained F: tcg/riscv64/ -F: disas/riscv.[ch] +F: disas/riscv*.[ch] =20 S390 TCG target M: Richard Henderson diff --git a/disas/meson.build b/disas/meson.build index bbfa119783..42977a1f74 100644 --- a/disas/meson.build +++ b/disas/meson.build @@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips= .c', 'nanomips.c')) common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files( 'riscv.c', 'riscv-xthead.c', - 'riscv-xventana.c' + 'riscv-xventana.c', + 'riscv-xlrbr.c' )) common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c')) common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c')) diff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c new file mode 100644 index 0000000000..57cb434523 --- /dev/null +++ b/disas/riscv-xlrbr.c @@ -0,0 +1,79 @@ +/* + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 + * bitmanip extension v0.93. + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "disas/riscv.h" +#include "disas/riscv-xlrbr.h" + +typedef enum { + /* 0 is reserved for rv_op_illegal. */ + rv_op_crc32_b =3D 1, + rv_op_crc32_h =3D 2, + rv_op_crc32_w =3D 3, + rv_op_crc32_d =3D 4, + rv_op_crc32c_b =3D 5, + rv_op_crc32c_h =3D 6, + rv_op_crc32c_w =3D 7, + rv_op_crc32c_d =3D 8, +} rv_xlrbr_op; + +const rv_opcode_data rv_xlrbr_opcode_data[] =3D { + { "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 }, + { "crc32.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.b", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.h", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.w", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, + { "crc32c.d", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 }, +}; + +void decode_xlrbr(rv_decode *dec, rv_isa isa) +{ + rv_inst inst =3D dec->inst; + rv_opcode op =3D rv_op_illegal; + + switch ((inst >> 0) & 0b1111111) { + case 0b0010011: + switch ((inst >> 12) & 0b111) { + case 0b001: + switch ((inst >> 20 & 0b111111111111)) { + case 0b011000010000: + op =3D rv_op_crc32_b; + break; + case 0b011000010001: + op =3D rv_op_crc32_h; + break; + case 0b011000010010: + op =3D rv_op_crc32_w; + break; + case 0b011000010011: + op =3D rv_op_crc32_d; + break; + case 0b011000011000: + op =3D rv_op_crc32c_b; + break; + case 0b011000011001: + op =3D rv_op_crc32c_h; + break; + case 0b011000011010: + op =3D rv_op_crc32c_w; + break; + case 0b011000011011: + op =3D rv_op_crc32c_d; + break; + } + break; + } + break; + } + dec->op =3D op; +} diff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h new file mode 100644 index 0000000000..939a69ea6d --- /dev/null +++ b/disas/riscv-xlrbr.h @@ -0,0 +1,19 @@ +/* + * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32 + * bitmanip extension v0.93. + * + * Copyright (c) 2023 Rivos Inc + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef DISAS_RISCV_XLRBR_H +#define DISAS_RISCV_XLRBR_H + +#include "disas/riscv.h" + +extern const rv_opcode_data rv_xlrbr_opcode_data[]; + +void decode_xlrbr(rv_decode *, rv_isa); + +#endif /* DISAS_RISCV_XLRBR_H */ diff --git a/disas/riscv.c b/disas/riscv.c index 6f2667482d..d416a4d6b3 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -26,6 +26,7 @@ /* Vendor extensions */ #include "disas/riscv-xthead.h" #include "disas/riscv-xventana.h" +#include "disas/riscv-xlrbr.h" =20 typedef enum { /* 0 is reserved for rv_op_illegal. */ @@ -5434,6 +5435,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, = rv_inst inst, { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair }, { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync }, { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondo= ps }, + { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr }, }; =20 for (size_t i =3D 0; i < ARRAY_SIZE(decoders); i++) { --=20 2.48.1