From nobody Tue Apr 7 20:26:48 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=zte.com.cn Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773286342441150.63823949020502; Wed, 11 Mar 2026 20:32:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Wlv-000731-OB; Wed, 11 Mar 2026 23:31:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Wlm-00072l-64; Wed, 11 Mar 2026 23:31:30 -0400 Received: from mxhk.zte.com.cn ([160.30.148.35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Wlh-000635-Va; Wed, 11 Mar 2026 23:31:29 -0400 Received: from mse-fl1.zte.com.cn (unknown [10.5.228.132]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mxhk.zte.com.cn (FangMail) with ESMTPS id 4fWY7G14B9z7QYS7; Thu, 12 Mar 2026 11:31:22 +0800 (CST) Received: from xaxapp01.zte.com.cn ([10.88.99.176]) by mse-fl1.zte.com.cn with SMTP id 62C3VGBa030435; Thu, 12 Mar 2026 11:31:16 +0800 (+08) (envelope-from liu.xuemei1@zte.com.cn) Received: from mapi (xaxapp01[null]) by mapi (Zmail) with MAPI id mid32; Thu, 12 Mar 2026 11:31:16 +0800 (CST) X-Zmail-TransId: 2af969b23384c35-69b27 X-Mailer: Zmail v1.0 Message-ID: <20260312113116862hj09dOlNxa3pdNvL3wnmm@zte.com.cn> In-Reply-To: <20260312112336983jY95IEDTtzVrPbyk-taP3@zte.com.cn> References: 20260312112336983jY95IEDTtzVrPbyk-taP3@zte.com.cn Date: Thu, 12 Mar 2026 11:31:16 +0800 (CST) Mime-Version: 1.0 From: To: , , , , , , , Cc: , , Subject: =?UTF-8?B?W1BBVENIIHYzIDMvM10gaHcvaW50Yy9pbXNpYzogQWRkIGluLWtlcm5lbCBpbXNpYyBzYXZlIGFuZCByZXN0b3JlIGZ1bmN0aW9u?= X-MAIL: mse-fl1.zte.com.cn 62C3VGBa030435 X-TLS: YES X-SPF-DOMAIN: zte.com.cn X-ENVELOPE-SENDER: liu.xuemei1@zte.com.cn X-SPF: None X-SOURCE-IP: 10.5.228.132 unknown Thu, 12 Mar 2026 11:31:22 +0800 X-Fangmail-Anti-Spam-Filtered: true X-Fangmail-MID-QID: 69B2338A.000/4fWY7G14B9z7QYS7 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=160.30.148.35; envelope-from=liu.xuemei1@zte.com.cn; helo=mxhk.zte.com.cn X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1773286344107154100 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xuemei Liu Add save and restore funtction if kvm_irqchip_in_kernel() return true, it is to get and set IMSIC irqchip state from KVM kernel. Signed-off-by: Xuemei Liu --- hw/intc/riscv_imsic.c | 171 +++++++++++++++++++++++++++++++--- include/hw/intc/riscv_imsic.h | 3 + include/qemu/bitops.h | 1 + migration/vmstate-types.c | 1 - 4 files changed, 161 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index 7c9a012033..1c9c706b03 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -34,6 +34,7 @@ #include "system/system.h" #include "system/kvm.h" #include "migration/vmstate.h" +#include "kvm/kvm_riscv.h" #define IMSIC_MMIO_PAGE_LE 0x00 #define IMSIC_MMIO_PAGE_BE 0x04 @@ -363,11 +364,16 @@ static void riscv_imsic_realize(DeviceState *dev, Err= or **errp) qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages); imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; - imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); - imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + } else { + imsic->nr_eix =3D 2 * BITS_TO_U64S(imsic->num_irqs); + imsic->eie =3D g_new0(uint32_t, imsic->nr_eix); + imsic->eip =3D g_new0(uint32_t, imsic->nr_eix); } + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, imsic, TYPE_RISCV_IMSIC, IMSIC_MMIO_SIZE(imsic->num_pages)); @@ -398,23 +404,17 @@ static const Property riscv_imsic_properties[] =3D { DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0), }; -static bool riscv_imsic_state_needed(void *opaque) +static bool riscv_imsic_emul_state_needed(void *opaque) { return !kvm_irqchip_in_kernel(); } -static const VMStateDescription vmstate_riscv_imsic =3D { - .name =3D "riscv_imsic", - .version_id =3D 2, - .minimum_version_id =3D 2, - .needed =3D riscv_imsic_state_needed, +static const VMStateDescription vmstate_riscv_imsic_emul =3D { + .name =3D "riscv_imsic_emul", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_imsic_emul_state_needed, .fields =3D (const VMStateField[]) { - VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState, - num_pages, 0, - vmstate_info_uint32, uint32_t), - VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState, - num_pages, 0, - vmstate_info_uint32, uint32_t), VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState, num_eistate, 0, vmstate_info_uint32, uint32_t), @@ -422,6 +422,149 @@ static const VMStateDescription vmstate_riscv_imsic = =3D { } }; +static bool riscv_imsic_in_kernel_state_needed(void *opaque) +{ + return kvm_irqchip_in_kernel(); +} + +static int riscv_imsic_in_kernel_pre_save(void *opaque) +{ + RISCVIMSICState *imsic =3D opaque; + RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); + bool is_32bit =3D riscv_cpu_is_32bit(rcpu); + uint32_t inc =3D 2; + uint64_t attr; + + if (is_32bit) { + inc =3D 1; + } + + if (kvm_irqchip_in_kernel()) { + for (uint32_t i =3D 0; i < imsic->nr_eix; i +=3D inc) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIE0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eie + i, false); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIP0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eip + i, false); + } + } + + return 0; +} + +static int riscv_imsic_in_kernel_post_load(void *opaque, int version_id) +{ + RISCVIMSICState *imsic =3D opaque; + RISCVCPU *rcpu =3D RISCV_CPU(cpu_by_arch_id(imsic->hartid)); + bool is_32bit =3D riscv_cpu_is_32bit(rcpu); + uint32_t inc =3D 2; + uint64_t attr; + + if (is_32bit) { + inc =3D 1; + } + + if (kvm_irqchip_in_kernel()) { + for (uint32_t i =3D 0; i < imsic->nr_eix; i +=3D inc) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIE0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eie + i, true); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIP0 + i); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eip + i, true); + } + } + + return 0; +} + +static const VMStateDescription vmstate_riscv_imsic_in_kernel =3D { + .name =3D "riscv_imsic_in_kernel", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D riscv_imsic_in_kernel_state_needed, + .pre_save =3D riscv_imsic_in_kernel_pre_save, + .post_load =3D riscv_imsic_in_kernel_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(eie, RISCVIMSICState, + nr_eix, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eip, RISCVIMSICState, + nr_eix, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static int riscv_imsic_pre_save(void *opaque) +{ + RISCVIMSICState *imsic =3D opaque; + uint64_t attr; + + if (kvm_irqchip_in_kernel()) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIDELIVERY); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eidelivery, false); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EITHRESHOLD); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eithreshold, false); + } + + return 0; +} + +static int riscv_imsic_post_load(void *opaque, int version_id) +{ + RISCVIMSICState *imsic =3D opaque; + uint64_t attr; + + if (kvm_irqchip_in_kernel()) { + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EIDELIVERY); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eidelivery, true); + + attr =3D KVM_DEV_RISCV_AIA_IMSIC_MKATTR(imsic->hartid, + ISELECT_IMSIC_EITHRESHOLD); + kvm_riscv_aia_access_reg(KVM_DEV_RISCV_AIA_GRP_IMSIC, attr, + imsic->eithreshold, true); + } + + return 0; +} + +static const VMStateDescription vmstate_riscv_imsic =3D { + .name =3D "riscv_imsic", + .version_id =3D 3, + .minimum_version_id =3D 3, + .pre_save =3D riscv_imsic_pre_save, + .post_load =3D riscv_imsic_post_load, + .fields =3D (const VMStateField[]) { + VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * const []) { + &vmstate_riscv_imsic_emul, + &vmstate_riscv_imsic_in_kernel, + NULL + } +}; + static void riscv_imsic_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h index fae999731d..2206d82e0c 100644 --- a/include/hw/intc/riscv_imsic.h +++ b/include/hw/intc/riscv_imsic.h @@ -54,12 +54,15 @@ struct RISCVIMSICState { uint32_t *eidelivery; uint32_t *eithreshold; uint32_t *eistate; + uint32_t *eip; + uint32_t *eie; /* config */ bool mmode; uint32_t hartid; uint32_t num_pages; uint32_t num_irqs; + uint32_t nr_eix; }; DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index c7b838a628..a7f86f2ee0 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -20,6 +20,7 @@ #define BITS_PER_LONG (sizeof (unsigned long) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(lo= ng)) #define BITS_TO_U32S(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(ui= nt32_t)) +#define BITS_TO_U64S(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(ui= nt64_t)) #define BIT(nr) (1UL << (nr)) #define BIT_ULL(nr) (1ULL << (nr)) diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c index 89cb211472..368a2922aa 100644 --- a/migration/vmstate-types.c +++ b/migration/vmstate-types.c @@ -599,7 +599,6 @@ const VMStateInfo vmstate_info_tmp =3D { * is an array of 'unsigned long', which may be either 32 or 64 bits. */ /* This is the number of 64 bit words sent over the wire */ -#define BITS_TO_U64S(nr) DIV_ROUND_UP(nr, 64) static int get_bitmap(QEMUFile *f, void *pv, size_t size, const VMStateField *field) { --=20 2.27.0