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Wed, 11 Mar 2026 21:32:18 -0700 (PDT) From: alistair23@gmail.com X-Google-Original-From: alistair.francis@wdc.com To: qemu-devel@nongnu.org, armbru@redhat.com, pbonzini@redhat.com, berrange@redhat.com, peterx@redhat.com, philmd@linaro.org Cc: alistair23@gmail.com, Alistair Francis Subject: [PATCH 2/7] hw/riscv: microchip_pfsoc: Don't call qdev_get_machine in soc init Date: Thu, 12 Mar 2026 14:31:53 +1000 Message-ID: <20260312043158.4191378-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260312043158.4191378-1-alistair.francis@wdc.com> References: <20260312043158.4191378-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773290002868154100 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Calling qdev_get_machine() in the soc_init function would result in the following assert ../hw/core/qdev.c:858: qdev_get_machine: Assertion `dev' failed. when trying to run ./qemu-system-riscv64 -S -display none -M virt -device microchip.pfsoc,= help as the machine wasn't created yet. We call qdev_get_machine() to obtain the number of CPUs in the machine. So instead of setting the CPU num-harts in the init function let's set it in realise where the machine will exist. Signed-off-by: Alistair Francis --- hw/riscv/microchip_pfsoc.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 4ff83e4940..73cc229c54 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -143,7 +143,6 @@ static const MemMapEntry microchip_pfsoc_memmap[] =3D { =20 static void microchip_pfsoc_soc_instance_init(Object *obj) { - MachineState *ms =3D MACHINE(qdev_get_machine()); MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(obj); =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); @@ -162,7 +161,9 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) =20 object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, TYPE_RISCV_HART_ARRAY); - qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); + /* Set the `num-harts` property later as the machine is potentially not + * created yet. + */ qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", TYPE_RISCV_CPU_SIFIVE_U54); @@ -204,6 +205,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) int i; =20 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); /* * The cluster must be realized after the RISC-V hart array container, --=20 2.53.0