From nobody Tue Apr 7 20:12:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773244294353691.3456194498157; Wed, 11 Mar 2026 08:51:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Lq0-0003Jk-Bj; Wed, 11 Mar 2026 11:51:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Lpg-0003A4-74; Wed, 11 Mar 2026 11:50:50 -0400 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net ([209.97.181.73]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Lpc-0001Zt-Pd; Wed, 11 Mar 2026 11:50:47 -0400 Received: from prodtpl.icoremail.net (unknown [10.12.1.20]) by hzbj-icmmx-7 (Coremail) with SMTP id AQAAfwBnbppNj7FpndwACA--.1400S2; Wed, 11 Mar 2026 23:50:37 +0800 (CST) Received: from phytium.com.cn (unknown [218.76.62.144]) by mail (Coremail) with SMTP id AQAAf8DwW5JGj7Fpf8UAAA--.812S4; Wed, 11 Mar 2026 23:50:36 +0800 (CST) From: Tao Tang To: Fabiano Rosas , Laurent Vivier , Paolo Bonzini Cc: qemu-devel@nongnu.org, qemu-arm@nongnu.org, Peter Maydell , Chen Baozi , Pierrick Bouvier , Chao Liu , Tao Tang Subject: [RFC v2 1/2] tests/qtest: Add attrs argument support to memory access commands Date: Wed, 11 Mar 2026 23:49:33 +0800 Message-Id: <20260311154934.1575429-2-tangtao1634@phytium.com.cn> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260311154934.1575429-1-tangtao1634@phytium.com.cn> References: <20260311154934.1575429-1-tangtao1634@phytium.com.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: AQAAf8DwW5JGj7Fpf8UAAA--.812S4 X-CM-SenderInfo: pwdqw3tdrrljuu6sx5pwlxzhxfrphubq/1tbiAQALBWmwb-oGPQAAs4 Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=tangtao163 4@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvAXoW3ZF18Gr4ktrWkXr48Aw13urg_yoW8CrWfuo WfKF1qy347Xwnruryq9r1kJrsrX3yUCr1qqws5tr1UKa409rn09ay3tFsxZFyjqayrGry8 XFs2qrWfWr4Iy3s3n29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXasCq-sGcSsGvf J3UbIjqfuFe4nvWSU8nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UU UUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=209.97.181.73; envelope-from=tangtao1634@phytium.com.cn; helo=zg8tmja5ljk3lje4ms43mwaa.icoremail.net X-Spam_score_int: -1 X-Spam_score: -0.2 X-Spam_bar: / X-Spam_report: (-0.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1773244296939154100 Content-Type: text/plain; charset="utf-8" Extend qtest memory access commands to accept an optional attrs argument. Supported attrs: - secure (ARM/x86-only, lowercase) - space=3Dnon-secure|secure|root|realm (ARM-only, lowercase) For memory commands, parse attrs and select AddressSpace via cpu_asidx_from_attrs(), then issue accesses with the corresponding MemTxAttrs. Expose matching libqtest APIs: - qtest_{read,write}{b,w,l,q}_attrs() - qtest_mem{read,write,set}_attrs() Also add libqtest-single wrappers for the *_attrs helpers. Signed-off-by: Tao Tang --- system/qtest.c | 266 ++++++++++++++++++++++++++++------ tests/qtest/libqtest-single.h | 61 ++++++++ tests/qtest/libqtest.c | 148 +++++++++++++++++++ tests/qtest/libqtest.h | 25 ++++ 4 files changed, 453 insertions(+), 47 deletions(-) diff --git a/system/qtest.c b/system/qtest.c index cf90cd53ad..dbf3a63c57 100644 --- a/system/qtest.c +++ b/system/qtest.c @@ -22,6 +22,7 @@ #include "hw/core/qdev.h" #include "hw/core/irq.h" #include "hw/core/cpu.h" +#include "hw/arm/arm-security.h" #include "qemu/accel.h" #include "system/cpu-timers.h" #include "qemu/config-file.h" @@ -218,6 +219,39 @@ static void *qtest_server_send_opaque; * B64_DATA is an arbitrarily long base64 encoded string. * If the sizes do not match, the data will be truncated. * + * Memory access with MemTxAttrs: + * """""""""""""""""""""""""""""" + * + * The following commands allow specifying memory transaction attributes, + * which is useful for testing devices that behave differently based on + * security state (e.g., ARM TrustZone/CCA or System Management Mode in x8= 6). + * + * The memory access commands above support one optional ATTRS argument: + * + * .. code-block:: none + * + * > writeb ADDR VALUE + * < OK + * > writeb ADDR VALUE secure + * < OK + * > writeb ADDR VALUE space=3Drealm + * < OK + * > readb ADDR secure + * < OK VALUE + * > readb ADDR space=3Droot + * < OK VALUE + * > read ADDR SIZE space=3Dsecure + * < OK DATA + * > write ADDR SIZE DATA secure + * < OK + * > memset ADDR SIZE VALUE space=3Dnon-secure + * < OK + * + * ``secure`` sets MemTxAttrs.secure=3D1 (x86/ARM). + * ``space=3D...`` is ARM-specific and accepts: + * non-secure, secure, root, realm. + * ``space=3Dnon-secure`` is equivalent to omitting ATTRS. + * * IRQ management: * """"""""""""""" * @@ -353,6 +387,135 @@ static void qtest_install_gpio_out_intercept(DeviceSt= ate *dev, const char *name, *disconnected =3D qdev_intercept_gpio_out(dev, icpt, name, n); } =20 +static bool qtest_parse_mem_attrs(CharFrontend *chr, const char *arg, + MemTxAttrs *attrs) +{ + if (!arg) { + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return true; + } + + if (strcmp(arg, "secure") =3D=3D 0) { + *attrs =3D (MemTxAttrs){ .secure =3D 1 }; + return true; + } + + if (strncmp(arg, "space=3D", 6) =3D=3D 0) { + const char *space =3D arg + 6; + ARMSecuritySpace sec_space; + + if (!target_arm() && !target_aarch64()) { + qtest_send(chr, "ERR space=3D<...> is ARM-specific\n"); + return false; + } + + if (strcmp(space, "non-secure") =3D=3D 0) { + *attrs =3D MEMTXATTRS_UNSPECIFIED; + return true; + } else if (strcmp(space, "secure") =3D=3D 0) { + sec_space =3D ARMSS_Secure; + } else if (strcmp(space, "root") =3D=3D 0) { + sec_space =3D ARMSS_Root; + } else if (strcmp(space, "realm") =3D=3D 0) { + sec_space =3D ARMSS_Realm; + } else { + qtest_send(chr, "ERR invalid space value. Valid space: " + "secure/non-secure/root/realm\n"); + return false; + } + + *attrs =3D (MemTxAttrs){ + .space =3D sec_space, + .secure =3D arm_space_is_secure(sec_space), + }; + return true; + } + + qtest_send(chr, "ERR invalid attrs argument\n"); + return false; +} + +static bool qtest_get_mem_as(CharFrontend *chr, MemTxAttrs attrs, + AddressSpace **as) +{ + int asidx; + + /* + * cpu_asidx_from_attrs mainly uses attrs to call ->asidx_from_attrs. = We use + * first_cpu as it's readily available. + */ + + asidx =3D cpu_asidx_from_attrs(first_cpu, attrs); + *as =3D cpu_get_address_space(first_cpu, asidx); + if (!*as) { + qtest_send(chr, "ERR address space unavailable for attrs\n"); + return false; + } + + return true; +} + +static void qtest_write_sized(AddressSpace *as, uint64_t addr, MemTxAttrs = attrs, + uint64_t value, char size) +{ + switch (size) { + case 'b': { + uint8_t data =3D value; + address_space_write(as, addr, attrs, &data, 1); + break; + } + case 'w': { + uint16_t data =3D value; + tswap16s(&data); + address_space_write(as, addr, attrs, &data, 2); + break; + } + case 'l': { + uint32_t data =3D value; + tswap32s(&data); + address_space_write(as, addr, attrs, &data, 4); + break; + } + case 'q': { + uint64_t data =3D value; + tswap64s(&data); + address_space_write(as, addr, attrs, &data, 8); + break; + } + default: + g_assert_not_reached(); + } +} + +static uint64_t qtest_read_sized(AddressSpace *as, uint64_t addr, + MemTxAttrs attrs, char size) +{ + switch (size) { + case 'b': { + uint8_t data; + address_space_read(as, addr, attrs, &data, 1); + return data; + } + case 'w': { + uint16_t data; + address_space_read(as, addr, attrs, &data, 2); + return tswap16(data); + } + case 'l': { + uint32_t data; + address_space_read(as, addr, attrs, &data, 4); + return tswap32(data); + } + case 'q': { + uint64_t data; + address_space_read(as, addr, attrs, &data, 8); + return tswap64(data); + } + default: + g_assert_not_reached(); + } +} + static void qtest_process_command(CharFrontend *chr, gchar **words) { const gchar *command; @@ -510,34 +673,25 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) strcmp(words[0], "writeq") =3D=3D 0) { uint64_t addr; uint64_t value; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2]); + if (words[3] && words[4]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &value); g_assert(ret =3D=3D 0); - - if (words[0][5] =3D=3D 'b') { - uint8_t data =3D value; - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 1); - } else if (words[0][5] =3D=3D 'w') { - uint16_t data =3D value; - tswap16s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 2); - } else if (words[0][5] =3D=3D 'l') { - uint32_t data =3D value; - tswap32s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 4); - } else if (words[0][5] =3D=3D 'q') { - uint64_t data =3D value; - tswap64s(&data); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - &data, 8); + if (!qtest_parse_mem_attrs(chr, words[3], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; } + + qtest_write_sized(as, addr, attrs, value, words[0][5]); qtest_send(chr, "OK\n"); } else if (strcmp(words[0], "readb") =3D=3D 0 || strcmp(words[0], "readw") =3D=3D 0 || @@ -545,50 +699,50 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) strcmp(words[0], "readq") =3D=3D 0) { uint64_t addr; uint64_t value =3D UINT64_C(-1); + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1]); + if (words[2] && words[3]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); - - if (words[0][4] =3D=3D 'b') { - uint8_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1); - value =3D data; - } else if (words[0][4] =3D=3D 'w') { - uint16_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 2); - value =3D tswap16(data); - } else if (words[0][4] =3D=3D 'l') { - uint32_t data; - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 4); - value =3D tswap32(data); - } else if (words[0][4] =3D=3D 'q') { - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &value, 8); - tswap64s(&value); + if (!qtest_parse_mem_attrs(chr, words[2], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; } + + value =3D qtest_read_sized(as, addr, attrs, words[0][4]); qtest_sendf(chr, "OK 0x%016" PRIx64 "\n", value); } else if (strcmp(words[0], "read") =3D=3D 0) { g_autoptr(GString) enc =3D NULL; uint64_t addr, len; uint8_t *data; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2]); + if (words[3] && words[4]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); /* We'd send garbage to libqtest if len is 0 */ g_assert(len); + if (!qtest_parse_mem_attrs(chr, words[3], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 data =3D g_malloc(len); - address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, da= ta, - len); + address_space_read(as, addr, attrs, data, len); =20 enc =3D qemu_hexdump_line(NULL, data, len, 0, 0); =20 @@ -619,13 +773,23 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) uint64_t addr, len, i; uint8_t *data; size_t data_len; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2] && words[3]); + if (words[4] && words[5]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); + if (!qtest_parse_mem_attrs(chr, words[4], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 data_len =3D strlen(words[3]); if (data_len < 3) { @@ -642,8 +806,7 @@ static void qtest_process_command(CharFrontend *chr, gc= har **words) data[i] =3D 0; } } - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, d= ata, - len); + address_space_write(as, addr, attrs, data, len); g_free(data); =20 qtest_send(chr, "OK\n"); @@ -651,26 +814,35 @@ static void qtest_process_command(CharFrontend *chr, = gchar **words) uint64_t addr, len; uint8_t *data; unsigned long pattern; + MemTxAttrs attrs; + AddressSpace *as; int ret; =20 g_assert(words[1] && words[2] && words[3]); + if (words[4] && words[5]) { + qtest_send(chr, "ERR too many arguments\n"); + return; + } ret =3D qemu_strtou64(words[1], NULL, 0, &addr); g_assert(ret =3D=3D 0); ret =3D qemu_strtou64(words[2], NULL, 0, &len); g_assert(ret =3D=3D 0); ret =3D qemu_strtoul(words[3], NULL, 0, &pattern); g_assert(ret =3D=3D 0); + if (!qtest_parse_mem_attrs(chr, words[4], &attrs) || + !qtest_get_mem_as(chr, attrs, &as)) { + return; + } =20 if (len) { data =3D g_malloc(len); memset(data, pattern, len); - address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIE= D, - data, len); + address_space_write(as, addr, attrs, data, len); g_free(data); } =20 qtest_send(chr, "OK\n"); - } else if (strcmp(words[0], "b64write") =3D=3D 0) { + } else if (strcmp(words[0], "b64write") =3D=3D 0) { uint64_t addr, len; uint8_t *data; size_t data_len; diff --git a/tests/qtest/libqtest-single.h b/tests/qtest/libqtest-single.h index 851724cbcb..38d05ee61e 100644 --- a/tests/qtest/libqtest-single.h +++ b/tests/qtest/libqtest-single.h @@ -291,6 +291,67 @@ static inline void memwrite(uint64_t addr, const void = *data, size_t size) qtest_memwrite(global_qtest, addr, data, size); } =20 +/* + * Memory commands with optional attrs argument. + */ +static inline void writeb_attrs(uint64_t addr, uint8_t value, const char *= attrs) +{ + qtest_writeb_attrs(global_qtest, addr, value, attrs); +} + +static inline void writew_attrs(uint64_t addr, uint16_t value, const char = *attrs) +{ + qtest_writew_attrs(global_qtest, addr, value, attrs); +} + +static inline void writel_attrs(uint64_t addr, uint32_t value, const char = *attrs) +{ + qtest_writel_attrs(global_qtest, addr, value, attrs); +} + +static inline void writeq_attrs(uint64_t addr, uint64_t value, const char = *attrs) +{ + qtest_writeq_attrs(global_qtest, addr, value, attrs); +} + +static inline uint8_t readb_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readb_attrs(global_qtest, addr, attrs); +} + +static inline uint16_t readw_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readw_attrs(global_qtest, addr, attrs); +} + +static inline uint32_t readl_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readl_attrs(global_qtest, addr, attrs); +} + +static inline uint64_t readq_attrs(uint64_t addr, const char *attrs) +{ + return qtest_readq_attrs(global_qtest, addr, attrs); +} + +static inline void memread_attrs(uint64_t addr, void *data, size_t size, + const char *attrs) +{ + qtest_memread_attrs(global_qtest, addr, data, size, attrs); +} + +static inline void memwrite_attrs(uint64_t addr, const void *data, size_t = size, + const char *attrs) +{ + qtest_memwrite_attrs(global_qtest, addr, data, size, attrs); +} + +static inline void memset_attrs(uint64_t addr, uint8_t pattern, size_t siz= e, + const char *attrs) +{ + qtest_memset_attrs(global_qtest, addr, pattern, size, attrs); +} + /** * clock_step_next: * diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 051faf31e1..a548331f7c 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1447,6 +1447,154 @@ void qtest_memset(QTestState *s, uint64_t addr, uin= t8_t pattern, size_t size) qtest_rsp(s); } =20 +static bool qtest_has_attrs(const char *attrs) +{ + return attrs && attrs[0]; +} + +static void qtest_write_attrs(QTestState *s, const char *cmd, + uint64_t addr, uint64_t value, + const char *attrs) +{ + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 " %s\n", + cmd, addr, value, attrs); + } else { + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 "\n", cmd, addr, valu= e); + } + qtest_rsp(s); +} + +static uint64_t qtest_read_attrs(QTestState *s, const char *cmd, + uint64_t addr, const char *attrs) +{ + gchar **args; + int ret; + uint64_t value; + + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "%s 0x%" PRIx64 " %s\n", cmd, addr, attrs); + } else { + qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr); + } + args =3D qtest_rsp_args(s, 2); + ret =3D qemu_strtou64(args[1], NULL, 0, &value); + g_assert(!ret); + g_strfreev(args); + + return value; +} + +void qtest_writeb_attrs(QTestState *s, uint64_t addr, uint8_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writeb", addr, value, attrs); +} + +void qtest_writew_attrs(QTestState *s, uint64_t addr, uint16_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writew", addr, value, attrs); +} + +void qtest_writel_attrs(QTestState *s, uint64_t addr, uint32_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writel", addr, value, attrs); +} + +void qtest_writeq_attrs(QTestState *s, uint64_t addr, uint64_t value, + const char *attrs) +{ + qtest_write_attrs(s, "writeq", addr, value, attrs); +} + +uint8_t qtest_readb_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readb", addr, attrs); +} + +uint16_t qtest_readw_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readw", addr, attrs); +} + +uint32_t qtest_readl_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readl", addr, attrs); +} + +uint64_t qtest_readq_attrs(QTestState *s, uint64_t addr, const char *attrs) +{ + return qtest_read_attrs(s, "readq", addr, attrs); +} + +void qtest_memread_attrs(QTestState *s, uint64_t addr, void *data, + size_t size, const char *attrs) +{ + uint8_t *ptr =3D data; + gchar **args; + size_t i; + + if (!size) { + return; + } + + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx %s\n", addr, size, attrs); + } else { + qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx\n", addr, size); + } + args =3D qtest_rsp_args(s, 2); + + for (i =3D 0; i < size; i++) { + ptr[i] =3D hex2nib(args[1][2 + (i * 2)]) << 4; + ptr[i] |=3D hex2nib(args[1][2 + (i * 2) + 1]); + } + + g_strfreev(args); +} + +void qtest_memwrite_attrs(QTestState *s, uint64_t addr, const void *data, + size_t size, const char *attrs) +{ + const uint8_t *ptr =3D data; + size_t i; + char *enc; + + if (!size) { + return; + } + + enc =3D g_malloc(2 * size + 1); + + for (i =3D 0; i < size; i++) { + sprintf(&enc[i * 2], "%02x", ptr[i]); + } + + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s %s\n", + addr, size, enc, attrs); + } else { + qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s\n", addr, size, enc= ); + } + qtest_rsp(s); + g_free(enc); +} + +void qtest_memset_attrs(QTestState *s, uint64_t addr, uint8_t pattern, + size_t size, const char *attrs) +{ + if (qtest_has_attrs(attrs)) { + qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x %s\n", + addr, size, pattern, attrs); + } else { + qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x\n", + addr, size, pattern); + } + qtest_rsp(s); +} + QDict *qtest_vqmp_assert_failure_ref(QTestState *qts, const char *fmt, va_list args) { diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index 9c118c89ca..d00a83478a 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -705,6 +705,31 @@ void qtest_bufwrite(QTestState *s, uint64_t addr, */ void qtest_memset(QTestState *s, uint64_t addr, uint8_t patt, size_t size); =20 +/* + * Memory commands with optional attrs argument. + */ + +void qtest_writeb_attrs(QTestState *s, uint64_t addr, uint8_t value, + const char *attrs); +void qtest_writew_attrs(QTestState *s, uint64_t addr, uint16_t value, + const char *attrs); +void qtest_writel_attrs(QTestState *s, uint64_t addr, uint32_t value, + const char *attrs); +void qtest_writeq_attrs(QTestState *s, uint64_t addr, uint64_t value, + const char *attrs); + +uint8_t qtest_readb_attrs(QTestState *s, uint64_t addr, const char *attrs); +uint16_t qtest_readw_attrs(QTestState *s, uint64_t addr, const char *attrs= ); +uint32_t qtest_readl_attrs(QTestState *s, uint64_t addr, const char *attrs= ); +uint64_t qtest_readq_attrs(QTestState *s, uint64_t addr, const char *attrs= ); + +void qtest_memread_attrs(QTestState *s, uint64_t addr, void *data, size_t = size, + const char *attrs); +void qtest_memwrite_attrs(QTestState *s, uint64_t addr, const void *data, + size_t size, const char *attrs); +void qtest_memset_attrs(QTestState *s, uint64_t addr, uint8_t patt, size_t= size, + const char *attrs); + /** * qtest_clock_step_next: * @s: #QTestState instance to operate on. --=20 2.34.1 From nobody Tue Apr 7 20:12:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773244285713169.4467210418387; Wed, 11 Mar 2026 08:51:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Lpy-0003Ga-Bg; Wed, 11 Mar 2026 11:51:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Lpf-00039t-Iy; Wed, 11 Mar 2026 11:50:50 -0400 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net ([209.97.181.73]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0Lpd-0001a3-BH; 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charset="utf-8" Add qtest-attrs-test to exercise qtest memory commands with optional attrs on aarch64 (virt, secure=3Don) and x86 (pc, tcg). The test covers: - ARM (virt machine): exercises all supported ARM security spaces (non-secure, secure, root, realm). - x86 (pc machine): exercises secure attrs accesses (SMM address-space path). The test also covers libqtest-single *_attrs shortcut wrappers and verifies that space=3Dnon-secure behaves like omitting attrs. Signed-off-by: Tao Tang --- tests/qtest/meson.build | 4 +- tests/qtest/qtest-attrs-test.c | 234 +++++++++++++++++++++++++++++++++ 2 files changed, 237 insertions(+), 1 deletion(-) create mode 100644 tests/qtest/qtest-attrs-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index be4fa627b5..c11759e23f 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -115,6 +115,7 @@ qtests_i386 =3D \ 'drive_del-test', 'cpu-plug-test', 'migration-test', + 'qtest-attrs-test', ] =20 if dbus_display and config_all_devices.has_key('CONFIG_VGA') @@ -270,7 +271,8 @@ qtests_aarch64 =3D \ ['arm-cpu-features', 'numa-test', 'boot-serial-test', - 'migration-test'] + 'migration-test', + 'qtest-attrs-test'] =20 qtests_s390x =3D \ qtests_filter + \ diff --git a/tests/qtest/qtest-attrs-test.c b/tests/qtest/qtest-attrs-test.c new file mode 100644 index 0000000000..ce204c2c95 --- /dev/null +++ b/tests/qtest/qtest-attrs-test.c @@ -0,0 +1,234 @@ +/* + * QTest for memory access with transaction attributes + * + * Verify optional attrs argument support for qtest memory commands. + * + * Copyright (c) 2026 Phytium Technology + * + * Author: + * Tao Tang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "libqtest-single.h" + +/* + * Default RAM size is 128 MiB on both machines used below. + * Keep test addresses in low RAM and away from device MMIO regions. + */ +#define TEST_ADDR_OFFSET 0x1000ULL +#define TEST_ARM_BASE 0x40000000ULL +#define TEST_X86_BASE 0x0ULL + +#define TEST_ADDR_ARM (TEST_ARM_BASE + TEST_ADDR_OFFSET) +#define TEST_ADDR_X86 (TEST_X86_BASE + TEST_ADDR_OFFSET) + +#define ARM_MACHINE_ARGS "-machine virt,secure=3Don -cpu cortex-a57" +#define X86_MACHINE_ARGS "-machine pc -accel tcg" + +static void test_arm_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x1, 0x22, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x1, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x22); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x2, 0x33, "space=3Drealm"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x2, "space=3Drealm"); + g_assert_cmpuint(val, =3D=3D, 0x33); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x3, 0x44, "space=3Droot"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x3, "space=3Droot"); + g_assert_cmpuint(val, =3D=3D, 0x44); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x4, 0x55, "space=3Dsecure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x4, "space=3Dsecure"); + g_assert_cmpuint(val, =3D=3D, 0x55); + + /* space=3Dnon-secure is equivalent to no attrs argument */ + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x5, 0x66, "space=3Dnon-secure= "); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x5, NULL); + g_assert_cmpuint(val, =3D=3D, 0x66); + + qtest_writeb_attrs(qts, TEST_ADDR_ARM + 0x6, 0x77, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_ARM + 0x6, "space=3Dnon-secur= e"); + g_assert_cmpuint(val, =3D=3D, 0x77); + + qtest_quit(qts); +} + +static void test_arm_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[16] =3D { + 0x00, 0x11, 0x22, 0x33, + 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, + 0xcc, 0xdd, 0xee, 0xff, + }; + uint8_t rbuf[16]; + size_t i; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qts =3D qtest_init(ARM_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM + 0x100, + wbuf, sizeof(wbuf), NULL); + qtest_memread_attrs(qts, TEST_ADDR_ARM + 0x100, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM + 0x200, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM + 0x200, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_ARM + 0x300, + wbuf, sizeof(wbuf), "space=3Drealm"); + qtest_memread_attrs(qts, TEST_ADDR_ARM + 0x300, + rbuf, sizeof(rbuf), "space=3Drealm"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_ARM + 0x400, + 0xa5, sizeof(rbuf), "space=3Droot"); + qtest_memread_attrs(qts, TEST_ADDR_ARM + 0x400, + rbuf, sizeof(rbuf), "space=3Droot"); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0xa5); + } + + qtest_memset_attrs(qts, TEST_ADDR_ARM + 0x500, + 0x5a, sizeof(rbuf), "space=3Dnon-secure"); + qtest_memread_attrs(qts, TEST_ADDR_ARM + 0x500, + rbuf, sizeof(rbuf), NULL); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x5a); + } + + qtest_quit(qts); +} + +static void test_arm_single_shortcuts_attrs(void) +{ + uint8_t val; + uint8_t wbuf[4] =3D { 0x10, 0x20, 0x30, 0x40 }; + uint8_t rbuf[4]; + + if (!qtest_has_machine("virt")) { + g_test_skip("virt machine not available"); + return; + } + + qtest_start(ARM_MACHINE_ARGS); + + writeb_attrs(TEST_ADDR_ARM + 0x600, 0x5a, "secure"); + val =3D readb_attrs(TEST_ADDR_ARM + 0x600, "secure"); + g_assert_cmpuint(val, =3D=3D, 0x5a); + + writel_attrs(TEST_ADDR_ARM + 0x604, + 0xa5a5a5a5, "space=3Drealm"); + g_assert_cmphex(readl_attrs(TEST_ADDR_ARM + 0x604, "space=3Drealm"), = =3D=3D, + 0xa5a5a5a5U); + + memwrite_attrs(TEST_ADDR_ARM + 0x608, + wbuf, sizeof(wbuf), "space=3Dnon-secure"); + memread_attrs(TEST_ADDR_ARM + 0x608, + rbuf, sizeof(rbuf), NULL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_end(); +} + +static void test_x86_scalar_attrs(void) +{ + QTestState *qts; + uint8_t val; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_writeb_attrs(qts, TEST_ADDR_X86, 0x11, NULL); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86, NULL); + g_assert_cmpuint(val, =3D=3D, 0x11); + + qtest_writeb_attrs(qts, TEST_ADDR_X86 + 0x1, 0xaa, "secure"); + val =3D qtest_readb_attrs(qts, TEST_ADDR_X86 + 0x1, "secure"); + g_assert_cmpuint(val, =3D=3D, 0xaa); + + qtest_quit(qts); +} + +static void test_x86_bulk_attrs(void) +{ + QTestState *qts; + uint8_t wbuf[8] =3D { 1, 2, 3, 4, 5, 6, 7, 8 }; + uint8_t rbuf[8]; + size_t i; + + if (!qtest_has_machine("pc")) { + g_test_skip("pc machine not available"); + return; + } + + qts =3D qtest_init(X86_MACHINE_ARGS); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x100, wbuf, sizeof(wbuf), N= ULL); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x100, rbuf, sizeof(rbuf), NU= LL); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memwrite_attrs(qts, TEST_ADDR_X86 + 0x180, + wbuf, sizeof(wbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x180, + rbuf, sizeof(rbuf), "secure"); + g_assert(memcmp(wbuf, rbuf, sizeof(wbuf)) =3D=3D 0); + + qtest_memset_attrs(qts, TEST_ADDR_X86 + 0x200, + 0x3c, sizeof(rbuf), "secure"); + qtest_memread_attrs(qts, TEST_ADDR_X86 + 0x200, + rbuf, sizeof(rbuf), "secure"); + for (i =3D 0; i < sizeof(rbuf); i++) { + g_assert_cmpuint(rbuf[i], =3D=3D, 0x3c); + } + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/qtest/arm/attrs/scalar", test_arm_scalar_attrs); + qtest_add_func("/qtest/arm/attrs/bulk", test_arm_bulk_attrs); + qtest_add_func("/qtest/arm/attrs/single_shortcuts", + test_arm_single_shortcuts_attrs); + + qtest_add_func("/qtest/x86/attrs/scalar", test_x86_scalar_attrs); + qtest_add_func("/qtest/x86/attrs/bulk", test_x86_bulk_attrs); + + return g_test_run(); +} --=20 2.34.1