From nobody Tue Apr 7 21:44:30 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1773241845; cv=none; d=zohomail.com; s=zohoarc; b=l1bRgJufmw4sVyzbcx4qDAxaoDGL5ggs/0h0Yc3nsn2JgpQ6COSysSePfpTx7kzmY4dam9uiHQlCrYgtCQT79n4AmYvK11Wk7IDaUdxCyvVPf3+fA8lZyNDZJwn3qnzFALqvQ06gFa1qgQoL2RiFHLRC/uru+YE7PK1IEEFFhMc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773241845; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/emhi+RMJR4D52cOf85+smcIzVpI0shy2Y+RZg1wWDI=; b=f0mQyzcuoRgPjAa6kmlHHoy4vwUEMsHBlSwADF5ejEldsduNEQjAllHglF3vaeBmP/J+C+Fsy9wK4nk2olF/xFifa4U0qSURSxY9jno73+b2dM8XEr8fcBSOB8x1PGk4aaCx7mlWxdbOiA7FuljdyFP6lz8PmB1Ge0g7JFAI5Z8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773241845620390.5680091720044; Wed, 11 Mar 2026 08:10:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0LBs-0001lr-SS; Wed, 11 Mar 2026 11:09:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0L9q-0004Kb-QA; Wed, 11 Mar 2026 11:07:40 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0L9o-0005NL-W0; Wed, 11 Mar 2026 11:07:34 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id AAEAD191E8D; Wed, 11 Mar 2026 18:04:41 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 99C4C37C2CE; Wed, 11 Mar 2026 18:05:19 +0300 (MSK) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=tls.msk.ru; s=202602; t=1773241481; bh=yQnZjgyMz3ySbNBJU7G+jkBzponQ6pRrFaMlgEJtwFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=j45f77DDIt6UyheXiIFKVj/jlT6PAv8AEeXx4L/pBC3Zi/gacCpf/rLzhL1JFXdaD 8JxgQ9c/sfmeItiyobzY5TlZUAE06be6cwLU1eUH22Cc38f84x2C26vtfC+TDwUTvn 3nFhJ29HygLL9CydM2vUm5cuK56mjPv0Vvq3zmNXhuRYe3YRImSlCm4CUFpRzPgMwo vKy76Boz+kllmybKeI8lSPx81C/IROYudRhUxEoPyXCg878V7bOeu4veqOgvMgDdCd PFDac/6gl2Sl3B/MWS90egpoz01SK0jCW1BAF4Cto11Clo72xln0lw8jWNLmlFbk4r CjM6mD008RVqw== From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Michael Tokarev Subject: [Stable-10.1.5 10/46] hw/i2c/aspeed_i2c: Fix out-of-bounds read in I2C MMIO handlers Date: Wed, 11 Mar 2026 18:02:46 +0300 Message-ID: <20260311150327.1084669-10-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -2 X-Spam_score: -0.3 X-Spam_bar: / X-Spam_report: (-0.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @tls.msk.ru) X-ZM-MESSAGEID: 1773241846457158500 From: Jamin Lin The ASPEED I2C controller exposes a per-bus MMIO window of 0x80 bytes on AST2600/AST1030/AST2700, but the backing regs[] array was sized for only 28 dwords (0x70 bytes). This allows guest reads in the range [0x70..0x7f] to index past the end of regs[]. Fix this by: - Sizing ASPEED_I2C_NEW_NUM_REG to match the 0x80-byte window (0x80 >> 2 =3D 32 dwords). - Avoiding an unconditional pre-read from regs[] in the legacy/new read handlers. Initialize the return value to -1 and only read regs[] for offsets that are explicitly handled/valid, leaving invalid offsets to return -1 with a guest error log. Signed-off-by: Jamin Lin Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3290 Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20260210024331.3984696-2-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater (cherry picked from commit c2c5beec42bf9872b37e78b9e259132df7435cb5) Signed-off-by: Michael Tokarev diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index c48fa2050b..c455c3eb7c 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -94,7 +94,7 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *bus= , hwaddr offset, unsigned size) { AspeedI2CClass *aic =3D ASPEED_I2C_GET_CLASS(bus->controller); - uint64_t value =3D bus->regs[offset / sizeof(*bus->regs)]; + uint64_t value =3D -1; =20 switch (offset) { case A_I2CD_FUN_CTRL: @@ -105,7 +105,7 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus *b= us, hwaddr offset, case A_I2CD_DEV_ADDR: case A_I2CD_POOL_CTRL: case A_I2CD_BYTE_BUF: - /* Value is already set, don't do anything. */ + value =3D bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CD_CMD: value =3D SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus-= >bus)); @@ -113,21 +113,20 @@ static uint64_t aspeed_i2c_bus_old_read(AspeedI2CBus = *bus, hwaddr offset, case A_I2CD_DMA_ADDR: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func= __); - value =3D -1; break; } + value =3D bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CD_DMA_LEN: if (!aic->has_dma) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA support\n", __func= __); - value =3D -1; + break; } + value =3D bus->regs[offset / sizeof(*bus->regs)]; break; - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, off= set); - value =3D -1; break; } =20 @@ -139,7 +138,7 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus *b= us, hwaddr offset, unsigned size) { AspeedI2CClass *aic =3D ASPEED_I2C_GET_CLASS(bus->controller); - uint64_t value =3D bus->regs[offset / sizeof(*bus->regs)]; + uint64_t value =3D -1; =20 switch (offset) { case A_I2CC_FUN_CTRL: @@ -159,13 +158,12 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus = *bus, hwaddr offset, case A_I2CS_CMD: case A_I2CS_INTR_CTRL: case A_I2CS_DMA_LEN_STS: - /* Value is already set, don't do anything. */ + case A_I2CS_INTR_STS: + value =3D bus->regs[offset / sizeof(*bus->regs)]; break; case A_I2CC_DMA_ADDR: value =3D extract64(bus->dma_dram_offset, 0, 32); break; - case A_I2CS_INTR_STS: - break; case A_I2CM_CMD: value =3D SHARED_FIELD_DP32(value, BUS_BUSY_STS, i2c_bus_busy(bus-= >bus)); break; @@ -176,13 +174,13 @@ static uint64_t aspeed_i2c_bus_new_read(AspeedI2CBus = *bus, hwaddr offset, if (!aic->has_dma64) { qemu_log_mask(LOG_GUEST_ERROR, "%s: No DMA 64 bits support\n", __func__); - value =3D -1; + break; } + value =3D bus->regs[offset / sizeof(*bus->regs)]; break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, off= set); - value =3D -1; break; } =20 diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 2daacc10ce..efe8b1a0c5 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -36,8 +36,7 @@ OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEE= D_I2C) #define ASPEED_I2C_NR_BUSSES 16 #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 #define ASPEED_I2C_BUS_POOL_SIZE 0x20 -#define ASPEED_I2C_OLD_NUM_REG 11 -#define ASPEED_I2C_NEW_NUM_REG 28 +#define ASPEED_I2C_NEW_NUM_REG (0x80 >> 2) =20 #define A_I2CD_M_STOP_CMD BIT(5) #define A_I2CD_M_RX_CMD BIT(3) --=20 2.47.3