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bh=T4awKrVCB/aZWgqUVw/PdrxRFMfaZJ5JiBQL3hHi8ZM=; b=In3INpO4RwJiLiSJ+uP1J2ACB2y/SpAX/qQaLq69BBLOLpsZFZ+X6Ry09yO8412hUXM8b2ju7p3/6fYsAGubCdKn6DTK5CkGmmT2TMyngzMFCkKfnncX6FbLXoy/VCWv1gTk5+itj1eUMSTDLujuX4zad1wxURq2RQQ3hLVckGSlBs3XIpnLScGQhPzOzxj9GAd7XCs2tydu6O0Dag0Q3XGjYF4SsELjABkftBWk0nB2kMBIMZ0Frx8IVhoBQ+WfljjAP4jCyut2isaIxwOZsceb4B9LtO8UHufq770/FVDpKogd1Myy3XTaZFKqgAL3L1qbeI9Z8CfbFGKcIAkRAg== From: Jamin Lin To: =?iso-8859-1?Q?C=E9dric_Le_Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: Jamin Lin , Troy Lee , Kane Chen , "flwu@google.com" , "nabihestefan@google.com" Subject: [PATCH v1 02/13] hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch Thread-Topic: [PATCH v1 02/13] hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch Thread-Index: AQHcsShagWXSol7ixEyYVsjaS3J/lg== Date: Wed, 11 Mar 2026 07:26:18 +0000 Message-ID: <20260311072614.1095587-3-jamin_lin@aspeedtech.com> References: <20260311072614.1095587-1-jamin_lin@aspeedtech.com> In-Reply-To: <20260311072614.1095587-1-jamin_lin@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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Signed-off-by: Jamin Lin --- hw/usb/hcd-ehci.c | 129 +++++++++++++++++++++++++--------------------- 1 file changed, 71 insertions(+), 58 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 57f930b099..e2ff0f5874 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -41,21 +41,23 @@ #define FRAME_TIMER_NS (NANOSECONDS_PER_SECOND / FRAME_TIMER_FREQ) #define UFRAME_TIMER_NS (FRAME_TIMER_NS / 8) =20 -#define NB_MAXINTRATE 8 // Max rate at which controller issues i= nts -#define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction -#define MAX_QH 100 // Max allowable queue heads in a chain +#define NB_MAXINTRATE 8 /* Max rate at which controller issues int= s */ +#define BUFF_SIZE (5 * 4096) /* Max bytes to transfer per transacti= on */ +#define MAX_QH 100 /* Max allowable queue heads in a chain = */ #define MIN_UFR_PER_TICK 24 /* Min frames to process when catching u= p */ #define PERIODIC_ACTIVE 512 /* Micro-frames */ =20 -/* Internal periodic / asynchronous schedule state machine states +/* + * Internal periodic / asynchronous schedule state machine states */ typedef enum { EST_INACTIVE =3D 1000, EST_ACTIVE, EST_EXECUTING, EST_SLEEPING, - /* The following states are internal to the state machine function - */ + /* + *The following states are internal to the state machine function + */ EST_WAITLISTHEAD, EST_FETCHENTRY, EST_FETCHQH, @@ -71,13 +73,13 @@ typedef enum { /* macros for accessing fields within next link pointer entry */ #define NLPTR_GET(x) ((x) & 0xffffffe0) #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3) -#define NLPTR_TBIT(x) ((x) & 1) // 1=3Dinvalid, 0=3Dvalid +#define NLPTR_TBIT(x) ((x) & 1) /* 1=3Dinvalid, 0=3Dvalid */ =20 /* link pointer types */ -#define NLPTR_TYPE_ITD 0 // isoc xfer descriptor -#define NLPTR_TYPE_QH 1 // queue head -#define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descrip= tor -#define NLPTR_TYPE_FSTN 3 // frame span traversal node +#define NLPTR_TYPE_ITD 0 /* isoc xfer descriptor */ +#define NLPTR_TYPE_QH 1 /* queue head */ +#define NLPTR_TYPE_STITD 2 /* split xaction, isoc xfer descrip= tor */ +#define NLPTR_TYPE_FSTN 3 /* frame span traversal node */ =20 #define SET_LAST_RUN_CLOCK(s) \ (s)->last_run_ns =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -88,10 +90,10 @@ typedef enum { =20 #define set_field(data, newval, field) do { \ uint32_t val =3D *data; \ - val &=3D ~ field##_MASK; \ + val &=3D ~field##_MASK; \ val |=3D ((newval) << field##_SH) & field##_MASK; \ *data =3D val; \ - } while(0) + } while (0) =20 static const char *ehci_state_names[] =3D { [EST_INACTIVE] =3D "INACTIVE", @@ -472,8 +474,10 @@ static bool ehci_verify_pid(EHCIQueue *q, EHCIqtd *qtd) } } =20 -/* Finish executing and writeback a packet outside of the regular - fetchqh -> fetchqtd -> execute -> writeback cycle */ +/* + * Finish executing and writeback a packet outside of the regular + * fetchqh -> fetchqtd -> execute -> writeback cycle + */ static void ehci_writeback_async_complete_packet(EHCIPacket *p) { EHCIQueue *q =3D p->queue; @@ -733,7 +737,7 @@ static void ehci_detach(USBPort *port) ehci_queues_rip_device(s, port->dev, 0); ehci_queues_rip_device(s, port->dev, 1); =20 - *portsc &=3D ~(PORTSC_CONNECT|PORTSC_PED|PORTSC_SUSPEND); + *portsc &=3D ~(PORTSC_CONNECT | PORTSC_PED | PORTSC_SUSPEND); *portsc |=3D PORTSC_CSC; =20 ehci_raise_irq(s, USBSTS_PCD); @@ -858,7 +862,7 @@ void ehci_reset(void *opaque) * Do the detach before touching portsc, so that it correctly gets sen= d to * us or to our companion based on PORTSC_POWNER before the reset. */ - for(i =3D 0; i < EHCI_PORTS; i++) { + for (i =3D 0; i < EHCI_PORTS; i++) { devs[i] =3D s->ports[i].dev; if (devs[i] && devs[i]->attached) { usb_detach(&s->ports[i]); @@ -877,7 +881,7 @@ void ehci_reset(void *opaque) s->astate =3D EST_INACTIVE; s->pstate =3D EST_INACTIVE; =20 - for(i =3D 0; i < EHCI_PORTS; i++) { + for (i =3D 0; i < EHCI_PORTS; i++) { if (s->companion_ports[i]) { s->portsc[i] =3D PORTSC_POWNER | PORTSC_PPOWER; } else { @@ -942,8 +946,9 @@ static void handle_port_owner_write(EHCIState *s, int p= ort, uint32_t owner) uint32_t *portsc =3D &s->portsc[port]; uint32_t orig; =20 - if (s->companion_ports[port] =3D=3D NULL) + if (s->companion_ports[port] =3D=3D NULL) { return; + } =20 owner =3D owner & PORTSC_POWNER; orig =3D *portsc & PORTSC_POWNER; @@ -988,7 +993,7 @@ static void ehci_port_write(void *ptr, hwaddr addr, trace_usb_ehci_port_reset(port, 1); } =20 - if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) { + if (!(val & PORTSC_PRESET) && (*portsc & PORTSC_PRESET)) { trace_usb_ehci_port_reset(port, 0); if (dev && dev->attached) { usb_port_reset(&s->ports[port]); @@ -1065,8 +1070,10 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, break; =20 case USBSTS: - val &=3D USBSTS_RO_MASK; // bits 6 through 31 are RO - ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC + /* bits 6 through 31 are RO */ + val &=3D USBSTS_RO_MASK; + /* bits 0 through 5 are R/WC */ + ehci_clear_usbsts(s, val); val =3D s->usbsts; ehci_update_irq(s); break; @@ -1131,8 +1138,7 @@ static void ehci_flush_qh(EHCIQueue *q) put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3); } =20 -// 4.10.2 - +/* 4.10.2 */ static int ehci_qh_do_overlay(EHCIQueue *q) { EHCIPacket *p =3D QTAILQ_FIRST(&q->packets); @@ -1145,8 +1151,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q) assert(p !=3D NULL); assert(p->qtdaddr =3D=3D q->qtdaddr); =20 - // remember values in fields to preserve in qh after overlay - + /* remember values in fields to preserve in qh after overlay */ dtoggle =3D q->qh.token & QTD_TOKEN_DTOGGLE; ping =3D q->qh.token & QTD_TOKEN_PING; =20 @@ -1170,7 +1175,7 @@ static int ehci_qh_do_overlay(EHCIQueue *q) } =20 if (!(q->qh.epchar & QH_EPCHAR_DTC)) { - // preserve QH DT bit + /* preserve QH DT bit */ q->qh.token &=3D ~QTD_TOKEN_DTOGGLE; q->qh.token |=3D dtoggle; } @@ -1397,9 +1402,7 @@ static int ehci_execute(EHCIPacket *p, const char *ac= tion) return 1; } =20 -/* 4.7.2 - */ - +/* 4.7.2 */ static int ehci_process_itd(EHCIState *ehci, EHCIitd *itd, uint32_t addr) @@ -1411,13 +1414,13 @@ static int ehci_process_itd(EHCIState *ehci, =20 ehci->periodic_sched_active =3D PERIODIC_ACTIVE; =20 - dir =3D(itd->bufptr[1] & ITD_BUFPTR_DIRECTION); + dir =3D (itd->bufptr[1] & ITD_BUFPTR_DIRECTION); devaddr =3D get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR); endp =3D get_field(itd->bufptr[0], ITD_BUFPTR_EP); max =3D get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT); mult =3D get_field(itd->bufptr[2], ITD_BUFPTR_MULT); =20 - for(i =3D 0; i < 8; i++) { + for (i =3D 0; i < 8; i++) { if (itd->transact[i] & ITD_XACT_ACTIVE) { pg =3D get_field(itd->transact[i], ITD_XACT_PGSEL); off =3D itd->transact[i] & ITD_XACT_OFFSET_MASK; @@ -1513,8 +1516,9 @@ static int ehci_process_itd(EHCIState *ehci, } =20 =20 -/* This state is the entry point for asynchronous schedule - * processing. Entry here constitutes a EHCI start event state (4.8.5) +/* + * This state is the entry point for asynchronous schedule + * processing. Entry here constitutes a EHCI start event state (4.8.5) */ static int ehci_state_waitlisthead(EHCIState *ehci, int async) { @@ -1531,7 +1535,7 @@ static int ehci_state_waitlisthead(EHCIState *ehci, = int async) ehci_queues_rip_unused(ehci, async); =20 /* Find the head of the list (4.9.1.1) */ - for(i =3D 0; i < MAX_QH; i++) { + for (i =3D 0; i < MAX_QH; i++) { if (get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2) < 0) { return 0; @@ -1564,8 +1568,9 @@ out: } =20 =20 -/* This state is the entry point for periodic schedule processing as - * well as being a continuation state for async processing. +/* + * This state is the entry point for periodic schedule processing as + * well as being a continuation state for async processing. */ static int ehci_state_fetchentry(EHCIState *ehci, int async) { @@ -1674,7 +1679,7 @@ static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci,= int async) =20 #if EHCI_DEBUG if (q->qhaddr !=3D q->qh.next) { - DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n", + DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\= n", q->qhaddr, q->qh.epchar & QH_EPCHAR_H, q->qh.token & QTD_TOKEN_HALT, @@ -1757,7 +1762,8 @@ static int ehci_state_fetchsitd(EHCIState *ehci, int = async) static int ehci_state_advqueue(EHCIQueue *q) { #if 0 - /* TO-DO: 4.10.2 - paragraph 2 + /* + * TO-DO: 4.10.2 - paragraph 2 * if I-bit is set to 1 and QH is not active * go to horizontal QH */ @@ -1935,8 +1941,10 @@ static int ehci_state_execute(EHCIQueue *q) return -1; } =20 - // TODO verify enough time remains in the uframe as in 4.4.1.1 - // TODO write back ptr to async list when done or out of time + /* + * TODO verify enough time remains in the uframe as in 4.4.1.1 + * TODO write back ptr to async list when done or out of time + */ =20 /* 4.10.3, bottom of page 82, go horizontal on transaction counter =3D= =3D 0 */ if (!q->async && q->transact_ctr =3D=3D 0) { @@ -2047,7 +2055,7 @@ static void ehci_advance_state(EHCIState *ehci, int a= sync) int again; =20 do { - switch(ehci_get_state(ehci, async)) { + switch (ehci_get_state(ehci, async)) { case EST_WAITLISTHEAD: again =3D ehci_state_waitlisthead(ehci, async); break; @@ -2126,21 +2134,20 @@ static void ehci_advance_state(EHCIState *ehci, int= async) ehci_reset(ehci); again =3D 0; } - } - while (again); + } while (again); } =20 static void ehci_advance_async_state(EHCIState *ehci) { const int async =3D 1; =20 - switch(ehci_get_state(ehci, async)) { + switch (ehci_get_state(ehci, async)) { case EST_INACTIVE: if (!ehci_async_enabled(ehci)) { break; } ehci_set_state(ehci, async, EST_ACTIVE); - // No break, fall through to ACTIVE + /* No break, fall through to ACTIVE */ =20 case EST_ACTIVE: if (!ehci_async_enabled(ehci)) { @@ -2164,7 +2171,8 @@ static void ehci_advance_async_state(EHCIState *ehci) ehci_set_state(ehci, async, EST_WAITLISTHEAD); ehci_advance_state(ehci, async); =20 - /* If the doorbell is set, the guest wants to make a change to the + /* + * If the doorbell is set, the guest wants to make a change to the * schedule. The host controller needs to release cached data. * (section 4.8.2) */ @@ -2191,13 +2199,13 @@ static void ehci_advance_periodic_state(EHCIState *= ehci) uint32_t list; const int async =3D 0; =20 - // 4.6 + /* 4.6 */ =20 - switch(ehci_get_state(ehci, async)) { + switch (ehci_get_state(ehci, async)) { case EST_INACTIVE: if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) { ehci_set_state(ehci, async, EST_ACTIVE); - // No break, fall through to ACTIVE + /* No break, fall through to ACTIVE */ } else break; =20 @@ -2221,7 +2229,7 @@ static void ehci_advance_periodic_state(EHCIState *eh= ci) =20 DPRINTF("PERIODIC state adv fr=3D%d. [%08X] -> %08X\n", ehci->frindex / 8, list, entry); - ehci_set_fetch_addr(ehci, async,entry); + ehci_set_fetch_addr(ehci, async, entry); ehci_set_state(ehci, async, EST_FETCHENTRY); ehci_advance_state(ehci, async); ehci_queues_rip_unused(ehci, async); @@ -2246,7 +2254,8 @@ static void ehci_update_frindex(EHCIState *ehci, int = uframes) ehci_raise_irq(ehci, USBSTS_FLR); } =20 - /* How many times will frindex roll over 0x4000 with this frame count? + /* + * How many times will frindex roll over 0x4000 with this frame count? * usbsts_frindex is decremented by 0x4000 on rollover until it reache= s 0 */ int rollovers =3D (ehci->frindex + uframes) / 0x4000; @@ -2326,8 +2335,9 @@ static void ehci_work_bh(void *opaque) ehci->async_stepdown++; } =20 - /* Async is not inside loop since it executes everything it can once - * called + /* + * Async is not inside loop since it executes everything it can once + * called */ if (ehci_async_enabled(ehci) || ehci->astate !=3D EST_INACTIVE) { need_timer++; @@ -2345,15 +2355,18 @@ static void ehci_work_bh(void *opaque) } =20 if (need_timer) { - /* If we've raised int, we speed up the timer, so that we quickly - * notice any new packets queued up in response */ + /* + * If we've raised int, we speed up the timer, so that we quickly + * notice any new packets queued up in response + */ if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) { expire_time =3D t_now + NANOSECONDS_PER_SECOND / (FRAME_TIMER_FREQ * 4); ehci->int_req_by_async =3D false; } else { - expire_time =3D t_now + (NANOSECONDS_PER_SECOND - * (ehci->async_stepdown+1) / FRAME_TIMER_FR= EQ); + expire_time =3D t_now + + (NANOSECONDS_PER_SECOND * (ehci->async_stepdown + 1) / + FRAME_TIMER_FREQ); } timer_mod(ehci->frame_timer, expire_time); } --=20 2.43.0