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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1773202151751154100 From: Brian Cain Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu.h | 5 +++ target/hexagon/cpu.c | 80 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index da96b52bd2a..3446910feb6 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -209,6 +209,11 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagon= State *env, uintptr_t pc); =20 #ifndef CONFIG_USER_ONLY +/* + * @return true if the @a thread_env hardware thread is + * not stopped. + */ +bool hexagon_thread_is_enabled(CPUHexagonState *thread_env); uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg); uint32_t hexagon_sreg_read(CPUHexagonState *env, uint32_t reg); void hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t v= al); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 2964d8a63f6..cc2b4c18001 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -16,6 +16,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu/qemu-print.h" #include "cpu.h" #include "internal.h" @@ -31,10 +32,12 @@ #include "hex_mmu.h" =20 #ifndef CONFIG_USER_ONLY +#include "macros.h" #include "sys_macros.h" #include "accel/tcg/cpu-ldst.h" #include "qemu/main-loop.h" #include "hex_interrupts.h" +#include "exec/cpu-interrupt.h" #endif =20 static void hexagon_v66_cpu_init(Object *obj) { } @@ -324,6 +327,32 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *= cs, cpu_env(cs)->gpr[HEX_REG_PC] =3D tb->pc; } =20 +#ifndef CONFIG_USER_ONLY +bool hexagon_thread_is_enabled(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + if (!cpu->globalregs) { + return true; + } + uint32_t modectl =3D + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_MODECTL, + env->threadId); + uint32_t thread_enabled_mask =3D GET_FIELD(MODECTL_E, modectl); + bool E_bit =3D thread_enabled_mask & (0x1 << env->threadId); + + return E_bit; +} + +static bool hexagon_cpu_has_work(CPUState *cs) +{ + CPUHexagonState *env =3D cpu_env(cs); + + return hexagon_thread_is_enabled(env) && + (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI + | CPU_INTERRUPT_K0_UNLOCK | CPU_INTERRUPT_TLB_UNLOCK)); +} +#endif + static void hexagon_restore_state_to_opc(CPUState *cs, const TranslationBlock *tb, const uint64_t *data) @@ -419,10 +448,58 @@ static int hexagon_cpu_mmu_index(CPUState *cs, bool i= fetch) return MMU_USER_IDX; } =20 +#if !defined(CONFIG_USER_ONLY) +static void hexagon_cpu_set_irq(void *opaque, int irq, int level) +{ + HexagonCPU *cpu =3D HEXAGON_CPU(opaque); + CPUState *cs =3D CPU(cpu); + CPUHexagonState *env =3D cpu_env(cs); + + switch (irq) { + case HEXAGON_CPU_IRQ_0 ... HEXAGON_CPU_IRQ_7: + qemu_log_mask(CPU_LOG_INT, "%s: irq %d, level %d\n", + __func__, irq, level); + if (level) { + hex_raise_interrupts(env, 1 << irq, CPU_INTERRUPT_HARD); + } + break; + default: + g_assert_not_reached(); + } +} +#endif + static void hexagon_cpu_init(Object *obj) { +#if !defined(CONFIG_USER_ONLY) + HexagonCPU *cpu =3D HEXAGON_CPU(obj); + qdev_init_gpio_in(DEVICE(cpu), hexagon_cpu_set_irq, 8); +#endif } =20 +#ifndef CONFIG_USER_ONLY + +static bool hexagon_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUHexagonState *env =3D cpu_env(cs); + if (interrupt_request & CPU_INTERRUPT_TLB_UNLOCK) { + cs->halted =3D false; + cpu_reset_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK); + return true; + } + if (interrupt_request & CPU_INTERRUPT_K0_UNLOCK) { + cs->halted =3D false; + cpu_reset_interrupt(cs, CPU_INTERRUPT_K0_UNLOCK); + return true; + } + if (interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_SWI)) { + return hex_check_interrupts(env); + } + return false; +} + +#endif + static const TCGCPUOps hexagon_tcg_ops =3D { /* MTTCG not yet supported: require strict ordering */ .guest_default_memory_order =3D TCG_MO_ALL, @@ -433,6 +510,9 @@ static const TCGCPUOps hexagon_tcg_ops =3D { .synchronize_from_tb =3D hexagon_cpu_synchronize_from_tb, .restore_state_to_opc =3D hexagon_restore_state_to_opc, .mmu_index =3D hexagon_cpu_mmu_index, +#if !defined(CONFIG_USER_ONLY) + .cpu_exec_interrupt =3D hexagon_cpu_exec_interrupt, +#endif /* !CONFIG_USER_ONLY */ }; =20 static void hexagon_cpu_class_init(ObjectClass *c, const void *data) --=20 2.34.1