From nobody Wed Apr 8 02:53:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1773202370; cv=none; d=zohomail.com; s=zohoarc; b=Ox0362dCMwK9h9Yfu8c2bStWpEjk1ICRPX7x4UcFVutpvGnX0h5EVAMvK8inwB5IJESM4YEDItb1WNur0YBszxWbBw11HAE1V4wFLqHYOTreuZjRtVQ/lIvoRfHPSGdhAkYGiOLCl/QBi8pZEaqiTQZMyVFNDHgrDx2/4YczETY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773202370; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ujbXerkLwNEJdCn8PiYlDtr9LvPDgVbI85lbUd+ol6A=; b=atF+CwZaKIvtOvW0JpC1H3EI632LVB3neKeqlSoJpTkuzb8QUR93Ug/be8wfUzVBG+T/W3d9tzrOGM8Jrmy8HmkHVrK6n/zhZqZRji+I4fEbo2p94Dz0xc5M8Ek60E+6INUaTsGVKH6QatSxLmhOeDkziIdhxB9ZxitOan1n3Sc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773202370722858.8559479582935; Tue, 10 Mar 2026 21:12:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0AsL-0000u0-UF; Wed, 11 Mar 2026 00:08:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Arz-0000mV-Gd for qemu-devel@nongnu.org; Wed, 11 Mar 2026 00:08:28 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0Arx-0008Uh-O2 for qemu-devel@nongnu.org; Wed, 11 Mar 2026 00:08:27 -0400 Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62B3VIrr614124 for ; Wed, 11 Mar 2026 04:08:24 GMT Received: from mail-oa1-f70.google.com (mail-oa1-f70.google.com [209.85.160.70]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4cu0jf03ad-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 04:08:24 +0000 (GMT) Received: by mail-oa1-f70.google.com with SMTP id 586e51a60fabf-40f192cf4b6so31273204fac.1 for ; Tue, 10 Mar 2026 21:08:24 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4177e5ea30asm998656fac.10.2026.03.10.21.08.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 21:08:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ujbXerkLwNEJdCn8PiYlDtr9LvPDgVbI85lbUd+ol6A=; b=LAfyY8yNgBz8aydB TLMlMnDAyzOkjOVAlgr3QbzC9k3eKOhF9CbOLBV6paVSKksjrupgUzYjmKoJYHHe XB+vV9HpbiNphafbtI0UEesrYLbg2bEGqsQNeHDaueIjwHC/FutYwzVJhlae5iRv SBlTLbl4DEPAbGm1qKbRzE1l5Gle8X60gEpwMEYPnFZvd1dRL9kv/h9VBY0NwIjq sIwfWb3j9QzgFmxjlak549Hp7ozmIbX0lfgrCcdlQyrxL1nvosHNz3SdpovvFV/f rz70ML4dJICIXTdM5xrd+LWPAGfp1KfDaQQSOIfRSBTeEnlYIrJmA4ap/Ezs4RJT /iGBdg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773202103; x=1773806903; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ujbXerkLwNEJdCn8PiYlDtr9LvPDgVbI85lbUd+ol6A=; b=Xy4o/DdobXO6C+9ZDyWl2iQot02rv30xddbgKLT96/euJR6GzXnaELqlyrulVYPw0+ MylRMHun/Mbp5xdTk8jwP717p3l4yOGkabE6ogN3wqK86xX/s5TkztmhSXEO0GyyxdCX SGeAlQo9kZ0vdR9Dl1tRM8k+CC6wltyn0nlKDVqataesfI/VOfXWootVPb2AhDz4OjNt slAeXnjSN422G+0zFVr55I598V2TAPOIFF33XEPEtwD0IiWR38kxH7accWikKg6FavC3 OJ5uRzEEG4keSLnOnxfjxk0PR70LF/CKghbpSvnF0KPJr7E9sDUvGYnLKb1/lI4UUN7a bqbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773202103; x=1773806903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=ujbXerkLwNEJdCn8PiYlDtr9LvPDgVbI85lbUd+ol6A=; b=uf6DAcpY2VgqAwZMAJgLAiHc1zQdLfGG6Eav4l2bs/xBXqf95jja782mvS6vtT3CTq rSWAMXitqpLjf5hUYxflpcTm71rpgCbprG984x2lcAfq/gD+8/5kYDnEeQfWBfR4dVqo yFH8Btgx1qjSALgqVmZh40Qi1mTwBmOJbjC9FVMetkPbZpohJ22Q+498HzddL0XVf5IO bf9ncTJCy1FTYJPPxsjvUnmrhbDvaBRxetm9a6UiUnE+kC3KkvMIZpnFBIyfOQzLo21D tFiA521vSpdFckYkvUUPMvQvUi8faYHpQBtCOG+OCocDfVHX438zIPmxEDqYPkbVNaWw D1/g== X-Gm-Message-State: AOJu0YwOCgAmac91R0yo+4H2xDDND0LpEwvNetz5CoWwAWZw5VV61s/n 5qGRa5zlXjBBNoktTt7YHjOdg7hbesMhT1x8hblTHIZRP5k2rfEsFFUfjk8jsXMTSKqYQIpv+Iw ljs/gLpp1k4uozj6NDfbeFhVkygboVp6P0AjV8+9UsyjwgfpQtuyU9rqGjIDKSnSxyQ== X-Gm-Gg: ATEYQzyc3VA+Hw0Q6kpz23EdYK84yqUzW23b06saGNwKgV/XvA13+ShgaXYi0jJ8Fjl lZPAjef3RRYHWE/egp9GHD0YGk08hb0a1oaSKGif1yJo5iZ+E+COFUMsGRDrwNX8Bl5QTVgzV4A 1EmLOXUsDLSXgHbhTb0uJKPEGXM2RaHnJoU5l4hPBVQQ5N7IFU0cxlPghIYuX/5X1C5stZEkGS3 XD/9f9GNUA/L5eT198BCI0KwlHefynglJjTxQuM2DoMcz37qsLfzcWl3Q6q2HhCG1mHxA8wxyLb 5N0RARoU1OHhGh0MwjjBohT4lXr8k2yvXUk3Aj7lnAGcj8YcoldH3D8ibA0KhBN4Af2rJiamEVo zvN6DZR6hdHiNfdimJ5OMmzrOIzoe9uZ0kzPiSNb/+EAxXdmptH0Snbdd0ZKLrARMUgTpJQ== X-Received: by 2002:a05:6870:40c1:b0:404:3cff:5158 with SMTP id 586e51a60fabf-4177c641969mr755503fac.16.1773202103400; Tue, 10 Mar 2026 21:08:23 -0700 (PDT) X-Received: by 2002:a05:6870:40c1:b0:404:3cff:5158 with SMTP id 586e51a60fabf-4177c641969mr755486fac.16.1773202102804; Tue, 10 Mar 2026 21:08:22 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng Subject: [PATCH v3 12/32] target/hexagon: Implement stack overflow exception Date: Tue, 10 Mar 2026 21:07:38 -0700 Message-Id: <20260311040758.1068731-13-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260311040758.1068731-1-brian.cain@oss.qualcomm.com> References: <20260311040758.1068731-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: 4bqROYhlaCF6OIGvTuIdPFw1QC0w4pKM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAzMiBTYWx0ZWRfXw4DmqwKBy3xl MtSJVz+1qhR676W8B7EY9N5yNMnzD6He/K3qVepYB5Qel9ax1Tec/sBIf3o1zlJap83fH3YFm9Q 3ZpiWzPs+LU+oDQtzUcqpgpD+VqUkbrgofKMiF/mzBb0W0L1u0mJjgJe5WaeeTCVo4FJHMzBv7/ 0pHLEPNQMJLvo/FbppMnZZywAIpS555MMW71tf6oj7zOx5rWDy+ORKfaR6wQ1FelcqVQer4T2Fd FelSWeSYRdeFvhQ5MOJBwDREi+6nlM2hYmTLzJNN9BG7RJQL0Z8bF2KIyalvZXy9sP5gK/lxMbH iaFiTSAwEgKLrnVsy70s1zPRfI/VVnRs0yP+UmG2PiiaPeBhV7lhMNscJOpprimYshXT3E6Zyv2 g7dHsSzE+uhFmbqvODCBzg/McH/acVa03CpF0z8i8b1eeu+Oi4+U3R4aageJi9Y8mZtcTVO6rLN uw1HH7vnESxiidcX7IA== X-Authority-Analysis: v=2.4 cv=FMMWBuos c=1 sm=1 tr=0 ts=69b0eab8 cx=c_pps a=nSjmGuzVYOmhOUYzIAhsAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=pfDKOobNdc7td_IuCocA:9 a=QEXdDO2ut3YA:10 a=1zu1i0D7hVQfj8NKfPKu:22 X-Proofpoint-ORIG-GUID: 4bqROYhlaCF6OIGvTuIdPFw1QC0w4pKM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 impostorscore=0 suspectscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110032 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1773202372078158500 Implement the frame limit check for system emulation mode. When allocframe computes a new stack pointer below FRAMELIMIT, raise a precise exception (HEX_CAUSE_STACK_LIMIT). The check is skipped in monitor mode. Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- target/hexagon/helper.h | 1 + target/hexagon/macros.h | 3 --- target/hexagon/sys_macros.h | 4 ++++ target/hexagon/translate.h | 2 ++ target/hexagon/genptr.c | 18 +++++++++++------- target/hexagon/op_helper.c | 34 ++++++++++++++++++++++++++++++++++ 6 files changed, 52 insertions(+), 10 deletions(-) diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 9ca87acfe63..ebcd471ec0a 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_2(probe_hvx_stores, void, env, int) DEF_HELPER_2(probe_pkt_scalar_hvx_stores, void, env, int) =20 #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_3(raise_stack_overflow, void, env, i32, i32) DEF_HELPER_2(swi, void, env, i32) DEF_HELPER_2(cswi, void, env, i32) DEF_HELPER_2(ciad, void, env, i32) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 26d3f7d8a4b..d3f2105c932 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -538,9 +538,6 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) =20 #ifdef CONFIG_USER_ONLY #define fFRAMECHECK(ADDR, EA) do { } while (0) /* Not modelled in linux-us= er */ -#else -/* System mode not implemented yet */ -#define fFRAMECHECK(ADDR, EA) g_assert_not_reached(); #endif =20 #ifdef QEMU_GENERATE diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index 364fcde7383..cbc857fa2f5 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -95,6 +95,10 @@ #define fTRAP(TRAPTYPE, IMM) \ register_trap_exception(env, TRAPTYPE, IMM, PC) =20 +#ifdef QEMU_GENERATE +#define fFRAMECHECK(ADDR, EA) gen_framecheck(ctx, ADDR, EA) +#endif + #define fVIRTINSN_SPSWAP(IMM, REG) #define fVIRTINSN_GETIE(IMM, REG) { REG =3D 0xdeafbeef; } #define fVIRTINSN_SETIE(IMM, REG) diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index e7acbae9ffa..82b327312ec 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -339,4 +339,6 @@ FIELD(PROBE_PKT_SCALAR_HVX_STORES, S0_IS_PRED, 3, 1) FIELD(PROBE_PKT_SCALAR_HVX_STORES, S1_IS_PRED, 4, 1) FIELD(PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX, 5, 2) =20 +void gen_framecheck(DisasContext *ctx, TCGv_i32 addr, TCGv_i32 ea); + #endif diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index bac63a42def..f32890f85c7 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -897,26 +897,30 @@ static void gen_load_frame(DisasContext *ctx, TCGv_i6= 4 frame, TCGv EA) tcg_gen_qemu_ld_i64(frame, EA, ctx->mem_idx, MO_LE | MO_UQ); } =20 -#ifndef CONFIG_HEXAGON_IDEF_PARSER /* Stack overflow check */ -static void gen_framecheck(TCGv EA, int framesize) +void gen_framecheck(DisasContext *ctx, TCGv_i32 addr, TCGv_i32 ea) { - /* Not modelled in linux-user mode */ - /* Placeholder for system mode */ #ifndef CONFIG_USER_ONLY - g_assert_not_reached(); + TCGLabel *ok =3D gen_new_label(); + tcg_gen_brcond_i32(TCG_COND_GEU, addr, hex_gpr[HEX_REG_FRAMELIMIT], ok= ); + gen_helper_raise_stack_overflow(tcg_env, + tcg_constant_i32(ctx->insn->slot), ea); + gen_set_label(ok); #endif } =20 +#ifndef CONFIG_HEXAGON_IDEF_PARSER static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize) { TCGv r30 =3D get_result_gpr(ctx, HEX_REG_FP); + TCGv_i32 new_r29 =3D tcg_temp_new_i32(); TCGv_i64 frame; tcg_gen_addi_tl(r30, r29, -8); frame =3D gen_frame_scramble(); gen_store8(tcg_env, r30, frame, ctx->insn->slot); - gen_framecheck(r30, framesize); - tcg_gen_subi_tl(r29, r30, framesize); + tcg_gen_subi_tl(new_r29, r30, framesize); + gen_framecheck(ctx, new_r29, hex_gpr[HEX_REG_PC]); + tcg_gen_mov_tl(r29, new_r29); } =20 static void gen_deallocframe(DisasContext *ctx, TCGv_i64 r31_30, TCGv r30) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 6dfc1269809..c5c638c132e 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1392,6 +1392,40 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32= _t uiV) } =20 #ifndef CONFIG_USER_ONLY +void HELPER(raise_stack_overflow)(CPUHexagonState *env, uint32_t slot, + uint32_t badva) +{ + /* + * Per section 7.3.1 of the V67 Programmer's Reference, + * stack limit exception isn't raised in monitor mode. + */ + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (GET_SSR_FIELD(SSR_EX, ssr) || + !GET_SSR_FIELD(SSR_UM, ssr)) { + return; + } + + CPUState *cs =3D env_cpu(env); + cs->exception_index =3D HEX_EVENT_PRECISE; + env->cause_code =3D HEX_CAUSE_STACK_LIMIT; + ASSERT_DIRECT_TO_GUEST_UNSET(env, cs->exception_index); + + if (slot =3D=3D 0) { + env->t_sreg[HEX_SREG_BADVA0] =3D badva; + SET_SSR_FIELD(env, SSR_V0, 1); + SET_SSR_FIELD(env, SSR_V1, 0); + SET_SSR_FIELD(env, SSR_BVS, 0); + } else if (slot =3D=3D 1) { + env->t_sreg[HEX_SREG_BADVA1] =3D badva; + SET_SSR_FIELD(env, SSR_V0, 0); + SET_SSR_FIELD(env, SSR_V1, 1); + SET_SSR_FIELD(env, SSR_BVS, 1); + } else { + g_assert_not_reached(); + } + cpu_loop_exit_restore(cs, 0); +} + void HELPER(ciad)(CPUHexagonState *env, uint32_t mask) { g_assert_not_reached(); --=20 2.34.1