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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1773202435982154100 From: Brian Cain The PCYCLE register is available in system mode, but only increments when the SYSCFG.PCYCLEEN field is set. The UPCYCLE register is available in user mode and we model it unconditionally in linux-user emulation, as if the system had enabled PCYCCLEEN. For now, the model is very crudely counting the sum of instructions executed among vCPUs, regardless of how the instructions were actually scheduled. This is sufficient for demonstrating a rough level of activity but will be particularly misleading for benchmarks and performance tuning. We may decide to revisit this model in order to give more a bit more fidelity, though without a cache model it would still be very far from accurate. Co-authored-by: Sid Manning Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- target/hexagon/cpu.h | 5 +++-- target/hexagon/translate.h | 2 ++ target/hexagon/cpu.c | 14 ++++++++++++++ target/hexagon/cpu_helper.c | 32 ++++++++++++++++++++++++++++---- target/hexagon/translate.c | 21 +++++++++++++++++++++ 5 files changed, 68 insertions(+), 6 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index ee2e5eeece2..da96b52bd2a 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -30,6 +30,7 @@ #include "cpu-qom.h" #include "exec/cpu-common.h" #include "exec/cpu-defs.h" +#include "exec/cpu-common.h" #include "hex_regs.h" #include "mmvec/mmvec.h" #include "hw/core/registerfields.h" @@ -38,8 +39,7 @@ #error "Hexagon does not support system emulation" #endif =20 -#ifndef CONFIG_USER_ONLY -#endif +#include "reg_fields.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 @@ -202,6 +202,7 @@ struct ArchCPU { =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) FIELD(TB_FLAGS, MMU_INDEX, 1, 3) +FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 7e528379db6..e7acbae9ffa 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -84,6 +84,8 @@ typedef struct DisasContext { TCGv new_pred_value[NUM_PREGS]; TCGv branch_taken; TCGv dczero_addr; + bool pcycle_enabled; + uint32_t num_cycles; } DisasContext; =20 bool is_gather_store_insn(DisasContext *ctx); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 20c4b82a970..1c8a188dec4 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -293,9 +293,23 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState= *cs) } =20 #ifndef CONFIG_USER_ONLY + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t syscfg =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG, + env->threadId) : 0; + + bool pcycle_enabled =3D extract32(syscfg, + reg_field_info[SYSCFG_PCYCLEEN].offset, + reg_field_info[SYSCFG_PCYCLEEN].width); + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, cpu_mmu_index(env_cpu(env), false)); + + if (pcycle_enabled) { + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, 1); + } #else + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, PCYCLE_ENABLED, true); hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); #endif =20 diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index 4860e4a6ab0..729ffa47eed 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -33,17 +33,31 @@ uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_e= nv, int index) =20 uint64_t hexagon_get_sys_pcycle_count(CPUHexagonState *env) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + if (!GET_SSR_FIELD(SSR_CE, ssr)) { + return 0; + } + uint64_t cycles =3D 0; + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *thread_env =3D cpu_env(cs); + cycles +=3D thread_env->t_cycle_count; + } + HexagonCPU *cpu =3D env_archcpu(env); + uint64_t base =3D cpu->globalregs ? + hexagon_globalreg_get_pcycle_base(cpu->globalregs) : 0; + return base + cycles; } =20 uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonState *env) { - g_assert_not_reached(); + return hexagon_get_sys_pcycle_count(env) >> 32; } =20 uint32_t hexagon_get_sys_pcycle_count_low(CPUHexagonState *env) { - g_assert_not_reached(); + return extract64(hexagon_get_sys_pcycle_count(env), 0, 32); } =20 void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, @@ -60,7 +74,17 @@ void hexagon_set_sys_pcycle_count_low(CPUHexagonState *e= nv, =20 void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t cycles) { - g_assert_not_reached(); + BQL_LOCK_GUARD(); + HexagonCPU *cpu =3D env_archcpu(env); + if (cpu->globalregs) { + hexagon_globalreg_set_pcycle_base(cpu->globalregs, cycles); + } + + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *thread_env =3D cpu_env(cs); + thread_env->t_cycle_count =3D 0; + } } =20 void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4df4226cbcb..e4d4dad8ffd 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -61,6 +61,7 @@ TCGv_i64 hex_store_val64[STORES_MAX]; TCGv hex_llsc_addr; TCGv hex_llsc_val; TCGv_i64 hex_llsc_val_i64; +TCGv_i64 hex_cycle_count; TCGv hex_vstore_addr[VSTORES_MAX]; TCGv hex_vstore_size[VSTORES_MAX]; TCGv hex_vstore_pending[VSTORES_MAX]; @@ -128,6 +129,16 @@ static void gen_exception_raw(int excp) gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); } =20 +#ifndef CONFIG_USER_ONLY +static inline void gen_pcycle_counters(DisasContext *ctx) +{ + if (ctx->pcycle_enabled) { + tcg_gen_addi_i64(hex_cycle_count, hex_cycle_count, ctx->num_cycles= ); + ctx->num_cycles =3D 0; + } +} +#endif + static void gen_exec_counters(DisasContext *ctx) { tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], @@ -136,6 +147,10 @@ static void gen_exec_counters(DisasContext *ctx) hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_HVX_CNT], hex_gpr[HEX_REG_QEMU_HVX_CNT], ctx->num_hvx_insns); + +#ifndef CONFIG_USER_ONLY + gen_pcycle_counters(ctx); +#endif } =20 static bool use_goto_tb(DisasContext *ctx, target_ulong dest) @@ -821,6 +836,7 @@ static void gen_commit_hvx(DisasContext *ctx) } } =20 +static const int PCYCLES_PER_PACKET =3D 3; static void update_exec_counters(DisasContext *ctx) { Packet *pkt =3D ctx->pkt; @@ -840,6 +856,7 @@ static void update_exec_counters(DisasContext *ctx) } =20 ctx->num_packets++; + ctx->num_cycles +=3D PCYCLES_PER_PACKET; ctx->num_insns +=3D num_real_insns; ctx->num_hvx_insns +=3D num_hvx_insns; } @@ -989,11 +1006,13 @@ static void hexagon_tr_init_disas_context(DisasConte= xtBase *dcbase, =20 ctx->mem_idx =3D FIELD_EX32(hex_flags, TB_FLAGS, MMU_INDEX); ctx->num_packets =3D 0; + ctx->num_cycles =3D 0; ctx->num_insns =3D 0; ctx->num_hvx_insns =3D 0; ctx->branch_cond =3D TCG_COND_NEVER; ctx->is_tight_loop =3D FIELD_EX32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP); ctx->short_circuit =3D hex_cpu->short_circuit; + ctx->pcycle_enabled =3D FIELD_EX32(hex_flags, TB_FLAGS, PCYCLE_ENABLED= ); } =20 static void hexagon_tr_tb_start(DisasContextBase *db, CPUState *cpu) @@ -1136,6 +1155,8 @@ void hexagon_translate_init(void) offsetof(CPUHexagonState, llsc_val), "llsc_val"); hex_llsc_val_i64 =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64"); + hex_cycle_count =3D tcg_global_mem_new_i64(tcg_env, + offsetof(CPUHexagonState, t_cycle_count), "t_cycle_count"); for (i =3D 0; i < STORES_MAX; i++) { snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); hex_store_addr[i] =3D tcg_global_mem_new(tcg_env, --=20 2.34.1