From nobody Wed Apr 8 02:52:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1773201116; cv=none; d=zohomail.com; s=zohoarc; b=QwsvQhMtxq+rEHxh8pnpK1gliVnO3v+Gcwr/zLs/G+anjBEzLzAvLHUVuFwksFT+uiqvlOqj2XikaxhMp0otMTk2dh/o2IbJFutEtkonTFLFImX0N2/co55aYJ9ipV948Bh4Tm+DwXbAnkPiBNbW028pl3kLT0ywIwpbijJPApA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773201116; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dZkbCGEE82n37HUmY7NOHqXAn8+Vs0cvdT6iMiBagLw=; b=QCq3+mJYT+YzkLFGLQT+mjjQHaR79jwOZj4jHaMFaTdjpqtx+E/oY8CuEzZoCtLe7/7xQjDM4dYVpNVWbi+kdwSBTxYlElQehlvgr300NvG5ihuuKK4XaU/IWaa4JCb2AW582DTB3w0BkDEtiCv1iMzSeQsdHkYqDjuupBgI3j4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773201116756394.35599609106487; Tue, 10 Mar 2026 20:51:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0AaY-0002Ng-Md; Tue, 10 Mar 2026 23:50:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0AaW-0002L3-Cx for qemu-devel@nongnu.org; Tue, 10 Mar 2026 23:50:24 -0400 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0AaT-0005rB-3t for qemu-devel@nongnu.org; Tue, 10 Mar 2026 23:50:23 -0400 Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62B2s8uT248601 for ; Wed, 11 Mar 2026 03:50:10 GMT Received: from mail-ot1-f71.google.com (mail-ot1-f71.google.com [209.85.210.71]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ctqv11rcs-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 03:50:10 +0000 (GMT) Received: by mail-ot1-f71.google.com with SMTP id 46e09a7af769-7d740d7e5a3so29720985a34.2 for ; Tue, 10 Mar 2026 20:50:09 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d76ae39b39sm946430a34.15.2026.03.10.20.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 20:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= dZkbCGEE82n37HUmY7NOHqXAn8+Vs0cvdT6iMiBagLw=; b=LWTPmPSSUl91LdCw CRuZJf6ByJo7Oc5Y5JG4ZRqfsT4E6WIfop+S4jsn8NMwf+j4zTCwINqO4S5l09r+ JNljcFVk8zqzVxh9Iq+zMCUpRW+89KH0RVhJuZI5YviTU4UuVO2yXGSjrc7Gwp+x v5vGQzTUAdTwt2bivN7Mui+rlsAGbsboxvJ5OF743+EEtxg5KMLfh9WIWQXJTvWK vIWrHqiSgR5vXL6RJlt1e4r9gulFsLJbFLCH+1PS8iZfRQ9Uwnp2Nl1dt6zDPUKp ibGYIPnFG8iQ7Hy+ZkfPPA783PKOi7fLqHu773GHCuqzl4n6cwPybIEkcS5BuHEv dRx6Ug== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773201009; x=1773805809; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dZkbCGEE82n37HUmY7NOHqXAn8+Vs0cvdT6iMiBagLw=; b=MgXXX4pQ17CiJru21hI1bGXXgDQh+qtb1scbDV6tLwIeaCr/mas4TyGOzP/ZmU/iJ1 ElCz+EydgdTQxINw92yAVRZxf3mjJ8jZlvi6ekYIpweMwKAuAyN+KB0GkZ680Ix+zIoJ 073blhd9RdXgSeN8hUat8nPKRgO8noa503nCQ9dPBSgUaMUccIXCS3CMI1F5WskNS+4H W1UYpvDR54wfeu9nJ5N1dGo9eSlMyKzVJnLMSFyR5lzpMfcDN+v3XU7jSSrOA8LCT63l bB59mNOpUJ4nEMV+HP5LYF76K9scBG1mHYt4nXBbMgTEfrjDVIuUV1LuGNaSrxRp+OMG IdgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773201009; x=1773805809; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dZkbCGEE82n37HUmY7NOHqXAn8+Vs0cvdT6iMiBagLw=; b=nI/KOWhDmaFWNOO7g059sbTEFxw8jgnZ3KmuG3SkpyxqNFCa/PrcIWwOYsakre8N5A 7GYCKbvS9hG8mCJNplYLfqXXL3GcE9aiASFFaSHp0ZBAc1eLCMRZ8tEkOgNueXUMPzJ2 whKJS5NDFx3x3J1mc8goGviSHYRF8s8I/sNpc5tGSILTvLSJ8F3itk99PUmLvSm6pRO/ ArUQF9olcX4vMroScJwuBPSpbhRvNaxSKFdlfZN23n9JtZFgQp82GDn3mOkLkic+5dzB eVJghG6+hW4HxqrtssP5refTmQKbsftZ+ruIfkF1UmJ8sBp8Zjl8B2zuQwWs1scOwlNM YIyw== X-Gm-Message-State: AOJu0YyAdml10G1LmgXdqhp4qgDObbmh1x5ONlboWDaVryKPHszI0nG8 b4swJ0ndBtAuh6VCZO52spsG5zd6p2+pUryaayouJKvtfktR4bAv2J9xFFc9WBafCiV8bzJsa6H t8a4EwYhmbjoXsoIsHqgcDY5MVlERHcCCssKSEsDAEU/4XbNLREX69ushXrspqNILJA== X-Gm-Gg: ATEYQzwfH79Mv0nsY9HOjJu7RuDRqIbrpSzwd3vB+qk6Yog1ipGVaRv1zn3YnCgsaGE P2Wy9xBoUKGx2jSyE4KsWf5ugO6DzYF0GHv7FeOZqgj7X6HJN4sx3IOM7tZYDphBDM5VYZu06Tn C0dojh+K7QvNusxj8EfFAmlJMhLqrNqj+fJNcmqJw69WKBe+wU8+/ksDJNEU7kBsCMR0h78tCNJ nwuIUiv0yVwvu/IqTZ79lvSS+QYzdcw299ICtqjof/FxM07MsFpcpxHlk4uumUD8N3mwuCLA1mi XC/1zkRi76uelx+j5J3rYQESGfiopvuBwmJOKx6yUJgka/lkfYfOzMHR63VvzZ+o/Cx9rdOGpCW zV+PfOtm6S2c2W+TazrlltaQYt4rnbMugGbSxHxSwYp1E24u+YJBzpUXkNRUF/jrxpL7hrw== X-Received: by 2002:a05:6830:6c17:b0:7ca:c7a2:c935 with SMTP id 46e09a7af769-7d76a79e74emr933953a34.35.1773201009185; Tue, 10 Mar 2026 20:50:09 -0700 (PDT) X-Received: by 2002:a05:6830:6c17:b0:7ca:c7a2:c935 with SMTP id 46e09a7af769-7d76a79e74emr933903a34.35.1773201007636; Tue, 10 Mar 2026 20:50:07 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng Subject: [PATCH v5 32/35] target/hexagon: Add stubs for modify_ssr/get_exe_mode Date: Tue, 10 Mar 2026 20:49:20 -0700 Message-Id: <20260311034923.1044737-33-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com> References: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAyOSBTYWx0ZWRfXxxSNxQLvzfrn qEXcS9s1H97s3RqFQm8ryxFHxrtBvJpJlEyGR+9SqXS/ft+NAZyEzcVyktzrFBphEIxYemhPGaN x6Pba5ALwHnwu7Ca9RsXQT6iXfCH4HDfZSUV01/xLjal7shdRJrme89FIhID8drHkFLf2Esz+Ru DhK0z3ZS6a0tMWOxVqWh60/BdAjtd4kWjkhDARZZeN8wxo2qMCVdMP8E50BOcbuBojO+MQC8uv0 +26dWs0NQ6F36cUj0viS5tTQnnEbc4uT8XmtXfVtTwySrVGzNWvq4NMQolrGQqyuXnDPtgnEXUF MlAE1AgAtzKxdYoHRDaaBji1tZ4EX9GGi3pTl4x8dRorvJd59siXhdUt6GDdrBdJQCaiO5xEbUi JZxBEQvRIfFPRBocHhGSiGRmDbafmYjOVTkZb5jeu70u0FwAj1Nymrm6PrJZ9hnZvB3ywUIQTuj J/ABg+7mZmaM7HiD7VA== X-Proofpoint-GUID: Kjee3esQ9WkrMuAJ0caUIk9OGKeic1T_ X-Authority-Analysis: v=2.4 cv=S5vUAYsP c=1 sm=1 tr=0 ts=69b0e672 cx=c_pps a=OI0sxtj7PyCX9F1bxD/puw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=wSQl6HbG2_iCLujeRWoA:9 a=QEXdDO2ut3YA:10 a=Z1Yy7GAxqfX1iEi80vsk:22 X-Proofpoint-ORIG-GUID: Kjee3esQ9WkrMuAJ0caUIk9OGKeic1T_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 malwarescore=0 adultscore=0 bulkscore=0 spamscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110029 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.180.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1773201118780154100 Add hex_mmu.[ch], cpu mode helpers, and additional includes/stubs that integrate the TLB device with the CPU model. Reviewed-by: Taylor Simpson Signed-off-by: Brian Cain --- target/hexagon/cpu-param.h | 4 + target/hexagon/cpu.h | 17 +++ target/hexagon/cpu_helper.h | 2 + target/hexagon/hex_mmu.h | 25 ++++ target/hexagon/internal.h | 9 ++ target/hexagon/sys_macros.h | 3 + target/hexagon/cpu.c | 25 ++++ target/hexagon/cpu_helper.c | 10 ++ target/hexagon/hex_mmu.c | 277 ++++++++++++++++++++++++++++++++++++ target/hexagon/translate.c | 2 +- 10 files changed, 373 insertions(+), 1 deletion(-) create mode 100644 target/hexagon/hex_mmu.h create mode 100644 target/hexagon/hex_mmu.c diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h index 1f0f22a7968..9eae7d2361c 100644 --- a/target/hexagon/cpu-param.h +++ b/target/hexagon/cpu-param.h @@ -18,7 +18,11 @@ #ifndef HEXAGON_CPU_PARAM_H #define HEXAGON_CPU_PARAM_H =20 +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 16 /* 64K pages */ +#else +#define TARGET_PAGE_BITS 12 /* 4K pages */ +#endif =20 #define TARGET_VIRT_ADDR_SPACE_BITS 32 =20 diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e39e6e39fec..d8092cb6fe7 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -38,6 +38,9 @@ #error "Hexagon does not support system emulation" #endif =20 +#ifndef CONFIG_USER_ONLY +#endif + #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 =20 @@ -51,6 +54,8 @@ #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU #ifndef CONFIG_USER_ONLY #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_K0_UNLOCK CPU_INTERRUPT_TGT_INT_1 +#define CPU_INTERRUPT_TLB_UNLOCK CPU_INTERRUPT_TGT_INT_2 =20 #define HEX_CPU_MODE_USER 1 #define HEX_CPU_MODE_GUEST 2 @@ -67,6 +72,12 @@ #define MMU_GUEST_IDX 1 #define MMU_KERNEL_IDX 2 =20 +typedef enum { + HEX_LOCK_UNLOCKED =3D 0, + HEX_LOCK_WAITING =3D 1, + HEX_LOCK_OWNER =3D 2, + HEX_LOCK_QUEUED =3D 3 +} hex_lock_state_t; #endif =20 =20 @@ -128,6 +139,10 @@ typedef struct CPUArchState { =20 /* This alias of CPUState.cpu_index is used by imported sources: */ uint32_t threadId; + hex_lock_state_t tlb_lock_state; + hex_lock_state_t k0_lock_state; + uint32_t tlb_lock_count; + uint32_t k0_lock_count; #endif uint32_t next_PC; target_ulong new_value_usr; @@ -177,12 +192,14 @@ struct ArchCPU { bool short_circuit; #ifndef CONFIG_USER_ONLY struct HexagonTLBState *tlb; + uint32_t htid; #endif }; =20 #include "cpu_bits.h" =20 FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1) +FIELD(TB_FLAGS, MMU_INDEX, 1, 3) =20 G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env, uint32_t exception, diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h index 1486a03c64a..18300657f3d 100644 --- a/target/hexagon/cpu_helper.h +++ b/target/hexagon/cpu_helper.h @@ -14,5 +14,7 @@ uint32_t hexagon_get_sys_pcycle_count_high(CPUHexagonStat= e *env); void hexagon_set_sys_pcycle_count(CPUHexagonState *env, uint64_t); void hexagon_set_sys_pcycle_count_low(CPUHexagonState *env, uint32_t); void hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t); +void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old); +int get_exe_mode(CPUHexagonState *env); =20 #endif diff --git a/target/hexagon/hex_mmu.h b/target/hexagon/hex_mmu.h new file mode 100644 index 00000000000..99ddb3736a2 --- /dev/null +++ b/target/hexagon/hex_mmu.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HEXAGON_MMU_H +#define HEXAGON_MMU_H + +#include "cpu.h" + +extern void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value); +extern uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_= t VA); +extern void hex_mmu_on(CPUHexagonState *env); +extern void hex_mmu_off(CPUHexagonState *env); +extern void hex_mmu_mode_change(CPUHexagonState *env); +extern bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA, + MMUAccessType access_type, hwaddr *PA, int = *prot, + uint64_t *size, int32_t *excp, int mmu_idx); +extern int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry, + uint64_t index); +extern void hex_tlb_lock(CPUHexagonState *env); +extern void hex_tlb_unlock(CPUHexagonState *env); +void dump_mmu(CPUHexagonState *env); +#endif diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 33d73ed18d1..4338914efb5 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -36,6 +36,15 @@ void G_NORETURN do_raise_exception(CPUHexagonState *env, uint32_t PC, uintptr_t retaddr); =20 +#define hexagon_cpu_mmu_enabled(env) ({ \ + HexagonCPU *cpu =3D env_archcpu(env); \ + cpu->globalregs ? \ + GET_SYSCFG_FIELD(SYSCFG_MMUEN, \ + hexagon_globalreg_read(cpu->globalregs, \ + HEX_SREG_SYSCFG, (env)->threadId)) : \ + 0; \ +}) + #ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_hexagon_cpu; #endif diff --git a/target/hexagon/sys_macros.h b/target/hexagon/sys_macros.h index f497d55bb81..364fcde7383 100644 --- a/target/hexagon/sys_macros.h +++ b/target/hexagon/sys_macros.h @@ -139,6 +139,9 @@ #define fDCINVIDX(REG) #define fDCINVA(REG) do { REG =3D REG; } while (0) /* Nothing to do in qem= u */ =20 +#define fSET_TLB_LOCK() hex_tlb_lock(env); +#define fCLEAR_TLB_LOCK() hex_tlb_unlock(env); + #define fTLB_IDXMASK(INDEX) \ ((INDEX) & (fPOW2_ROUNDUP( \ fCAST4u(hexagon_tlb_get_num_entries(env_archcpu(env)->tlb))) - 1)) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 32d158684a0..5c937fa1cd1 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -27,6 +27,13 @@ #include "tcg/tcg.h" #include "exec/gdbstub.h" #include "accel/tcg/cpu-ops.h" +#include "cpu_helper.h" +#include "hex_mmu.h" + +#ifndef CONFIG_USER_ONLY +#include "sys_macros.h" +#include "accel/tcg/cpu-ldst.h" +#endif =20 static void hexagon_v66_cpu_init(Object *obj) { } static void hexagon_v67_cpu_init(Object *obj) { } @@ -54,6 +61,7 @@ static const Property hexagon_cpu_properties[] =3D { #if !defined(CONFIG_USER_ONLY) DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB, HexagonTLBState *), + DEFINE_PROP_UINT32("htid", HexagonCPU, htid, 0), #endif DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, @@ -280,6 +288,13 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState= *cs) hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } =20 +#ifndef CONFIG_USER_ONLY + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, + cpu_mmu_index(env_cpu(env), false)); +#else + hex_flags =3D FIELD_DP32(hex_flags, TB_FLAGS, MMU_INDEX, MMU_USER_IDX); +#endif + return (TCGTBCPUState){ .pc =3D pc, .flags =3D hex_flags }; } =20 @@ -297,6 +312,7 @@ static void hexagon_restore_state_to_opc(CPUState *cs, cpu_env(cs)->gpr[HEX_REG_PC] =3D data[0]; } =20 + static void hexagon_cpu_reset_hold(Object *obj, ResetType type) { CPUState *cs =3D CPU(obj); @@ -315,7 +331,15 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetT= ype type) memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); env->wait_next_pc =3D 0; + env->tlb_lock_state =3D HEX_LOCK_UNLOCKED; + env->k0_lock_state =3D HEX_LOCK_UNLOCKED; + env->tlb_lock_count =3D 0; + env->k0_lock_count =3D 0; env->next_PC =3D 0; + + HexagonCPU *cpu =3D HEXAGON_CPU(cs); + env->t_sreg[HEX_SREG_HTID] =3D cpu->htid; + env->threadId =3D cpu->htid; #endif env->cause_code =3D HEX_EVENT_NONE; } @@ -344,6 +368,7 @@ static void hexagon_cpu_realize(DeviceState *dev, Error= **errp) gdb_find_static_feature("hexagon-hvx.xml"), 0= ); =20 qemu_init_vcpu(cs); + cpu_reset(cs); mcc->parent_realize(dev, errp); } diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c index b8e0625e3f8..b6a8bd35309 100644 --- a/target/hexagon/cpu_helper.c +++ b/target/hexagon/cpu_helper.c @@ -58,3 +58,13 @@ void hexagon_set_sys_pcycle_count(CPUHexagonState *env, = uint64_t cycles) { g_assert_not_reached(); } + +void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old) +{ + g_assert_not_reached(); +} + +int get_exe_mode(CPUHexagonState *env) +{ + g_assert_not_reached(); +} diff --git a/target/hexagon/hex_mmu.c b/target/hexagon/hex_mmu.c new file mode 100644 index 00000000000..1cdc92fdc31 --- /dev/null +++ b/target/hexagon/hex_mmu.c @@ -0,0 +1,277 @@ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/main-loop.h" +#include "qemu/qemu-print.h" +#include "cpu.h" +#include "system/cpus.h" +#include "internal.h" +#include "exec/cpu-interrupt.h" +#include "cpu_helper.h" +#include "exec/cputlb.h" +#include "hex_mmu.h" +#include "macros.h" +#include "sys_macros.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/hexagon/hexagon_globalreg.h" + +static inline void hex_log_tlbw(uint32_t index, uint64_t entry) +{ + if (qemu_loglevel_mask(CPU_LOG_MMU)) { + if (qemu_log_enabled()) { + FILE *logfile =3D qemu_log_trylock(); + if (logfile) { + fprintf(logfile, "tlbw[%03d]: ", index); + if (!hexagon_tlb_dump_entry(logfile, entry)) { + fprintf(logfile, "invalid\n"); + } + qemu_log_unlock(logfile); + } + } + } +} + +void hex_tlbw(CPUHexagonState *env, uint32_t index, uint64_t value) +{ + uint32_t myidx =3D fTLB_NONPOW2WRAP(fTLB_IDXMASK(index)); + HexagonTLBState *tlb =3D env_archcpu(env)->tlb; + uint64_t old_entry =3D hexagon_tlb_read(tlb, myidx); + + bool old_entry_valid =3D extract64(old_entry, 63, 1); + if (old_entry_valid && hexagon_cpu_mmu_enabled(env)) { + CPUState *cs =3D env_cpu(env); + tlb_flush(cs); + } + hexagon_tlb_write(tlb, myidx, value); + hex_log_tlbw(myidx, value); +} + +void hex_mmu_on(CPUHexagonState *env) +{ + CPUState *cs =3D env_cpu(env); + qemu_log_mask(CPU_LOG_MMU, "Hexagon MMU turned on!\n"); + tlb_flush(cs); +} + +void hex_mmu_off(CPUHexagonState *env) +{ + CPUState *cs =3D env_cpu(env); + qemu_log_mask(CPU_LOG_MMU, "Hexagon MMU turned off!\n"); + tlb_flush(cs); +} + +void hex_mmu_mode_change(CPUHexagonState *env) +{ + qemu_log_mask(CPU_LOG_MMU, "Hexagon mode change!\n"); + CPUState *cs =3D env_cpu(env); + tlb_flush(cs); +} + +bool hex_tlb_find_match(CPUHexagonState *env, uint32_t VA, + MMUAccessType access_type, hwaddr *PA, int *prot, + uint64_t *size, int32_t *excp, int mmu_idx) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t ssr =3D env->t_sreg[HEX_SREG_SSR]; + uint8_t asid =3D GET_SSR_FIELD(SSR_ASID, ssr); + int cause_code =3D 0; + + bool found =3D hexagon_tlb_find_match(cpu->tlb, asid, VA, access_type, + PA, prot, size, excp, &cause_code, + mmu_idx); + if (cause_code) { + env->cause_code =3D cause_code; + } + return found; +} + +/* Called from tlbp instruction */ +uint32_t hex_tlb_lookup(CPUHexagonState *env, uint32_t ssr, uint32_t VA) +{ + HexagonCPU *cpu =3D env_archcpu(env); + uint8_t asid =3D GET_SSR_FIELD(SSR_ASID, ssr); + int cause_code =3D 0; + + uint32_t result =3D hexagon_tlb_lookup(cpu->tlb, asid, VA, &cause_code= ); + if (cause_code) { + env->cause_code =3D cause_code; + } + return result; +} + +/* + * Return codes: + * 0 or positive index of match + * -1 multiple matches + * -2 no match + */ +int hex_tlb_check_overlap(CPUHexagonState *env, uint64_t entry, uint64_t i= ndex) +{ + HexagonCPU *cpu =3D env_archcpu(env); + return hexagon_tlb_check_overlap(cpu->tlb, entry, index); +} + +void dump_mmu(CPUHexagonState *env) +{ + HexagonCPU *cpu =3D env_archcpu(env); + hexagon_tlb_dump(cpu->tlb); +} + +static inline void print_thread(const char *str, CPUState *cs) +{ + g_assert(bql_locked()); + CPUHexagonState *thread =3D cpu_env(cs); + bool is_stopped =3D cpu_is_stopped(cs); + int exe_mode =3D get_exe_mode(thread); + hex_lock_state_t lock_state =3D thread->tlb_lock_state; + qemu_log_mask(CPU_LOG_MMU, + "%s: threadId =3D %d: %s, exe_mode =3D %s, tlb_lock_state =3D %= s\n", + str, + thread->threadId, + is_stopped ? "stopped" : "running", + exe_mode =3D=3D HEX_EXE_MODE_OFF ? "off" : + exe_mode =3D=3D HEX_EXE_MODE_RUN ? "run" : + exe_mode =3D=3D HEX_EXE_MODE_WAIT ? "wait" : + exe_mode =3D=3D HEX_EXE_MODE_DEBUG ? "debug" : + "unknown", + lock_state =3D=3D HEX_LOCK_UNLOCKED ? "unlocked" : + lock_state =3D=3D HEX_LOCK_WAITING ? "waiting" : + lock_state =3D=3D HEX_LOCK_OWNER ? "owner" : + "unknown"); +} + +static inline void print_thread_states(const char *str) +{ + CPUState *cs; + CPU_FOREACH(cs) { + print_thread(str, cs); + } +} + +void hex_tlb_lock(CPUHexagonState *env) +{ + qemu_log_mask(CPU_LOG_MMU, "hex_tlb_lock: " TARGET_FMT_ld "\n", + env->threadId); + BQL_LOCK_GUARD(); + g_assert((env->tlb_lock_count =3D=3D 0) || (env->tlb_lock_count =3D=3D= 1)); + + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t syscfg =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG, + env->threadId) : 0; + uint8_t tlb_lock =3D GET_SYSCFG_FIELD(SYSCFG_TLBLOCK, syscfg); + if (tlb_lock) { + if (env->tlb_lock_state =3D=3D HEX_LOCK_QUEUED) { + env->next_PC +=3D 4; + env->tlb_lock_count++; + env->tlb_lock_state =3D HEX_LOCK_OWNER; + SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1); + return; + } + if (env->tlb_lock_state =3D=3D HEX_LOCK_OWNER) { + qemu_log_mask(CPU_LOG_MMU | LOG_GUEST_ERROR, + "Double tlblock at PC: 0x%x, thread may hang\n", + env->next_PC); + env->next_PC +=3D 4; + CPUState *cs =3D env_cpu(env); + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + return; + } + env->tlb_lock_state =3D HEX_LOCK_WAITING; + CPUState *cs =3D env_cpu(env); + cpu_interrupt(cs, CPU_INTERRUPT_HALT); + } else { + env->next_PC +=3D 4; + env->tlb_lock_count++; + env->tlb_lock_state =3D HEX_LOCK_OWNER; + SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 1); + } + + if (qemu_loglevel_mask(CPU_LOG_MMU)) { + qemu_log_mask(CPU_LOG_MMU, "Threads after hex_tlb_lock:\n"); + print_thread_states("\tThread"); + } +} + +void hex_tlb_unlock(CPUHexagonState *env) +{ + BQL_LOCK_GUARD(); + g_assert((env->tlb_lock_count =3D=3D 0) || (env->tlb_lock_count =3D=3D= 1)); + + /* Nothing to do if the TLB isn't locked by this thread */ + HexagonCPU *cpu =3D env_archcpu(env); + uint32_t syscfg =3D cpu->globalregs ? + hexagon_globalreg_read(cpu->globalregs, HEX_SREG_SYSCFG, + env->threadId) : 0; + uint8_t tlb_lock =3D GET_SYSCFG_FIELD(SYSCFG_TLBLOCK, syscfg); + if ((tlb_lock =3D=3D 0) || + (env->tlb_lock_state !=3D HEX_LOCK_OWNER)) { + qemu_log_mask(LOG_GUEST_ERROR, + "thread %d attempted to tlbunlock without having the= " + "lock, tlb_lock state =3D %d\n", + env->threadId, env->tlb_lock_state); + g_assert(env->tlb_lock_state !=3D HEX_LOCK_WAITING); + return; + } + + env->tlb_lock_count--; + env->tlb_lock_state =3D HEX_LOCK_UNLOCKED; + SET_SYSCFG_FIELD(env, SYSCFG_TLBLOCK, 0); + + /* Look for a thread to unlock */ + unsigned int this_threadId =3D env->threadId; + CPUHexagonState *unlock_thread =3D NULL; + CPUState *cs; + CPU_FOREACH(cs) { + CPUHexagonState *thread =3D cpu_env(cs); + + /* + * The hardware implements round-robin fairness, so we look for th= reads + * starting at env->threadId + 1 and incrementing modulo the numbe= r of + * threads. + * + * To implement this, we check if thread is a earlier in the modulo + * sequence than unlock_thread. + * if unlock thread is higher than this thread + * thread must be between this thread and unlock_thread + * else + * thread higher than this thread is ahead of unlock_thread + * thread must be lower then unlock thread + */ + if (thread->tlb_lock_state =3D=3D HEX_LOCK_WAITING) { + if (!unlock_thread) { + unlock_thread =3D thread; + } else if (unlock_thread->threadId > this_threadId) { + if (this_threadId < thread->threadId && + thread->threadId < unlock_thread->threadId) { + unlock_thread =3D thread; + } + } else { + if (thread->threadId > this_threadId) { + unlock_thread =3D thread; + } + if (thread->threadId < unlock_thread->threadId) { + unlock_thread =3D thread; + } + } + } + } + if (unlock_thread) { + cs =3D env_cpu(unlock_thread); + print_thread("\tWaiting thread found", cs); + unlock_thread->tlb_lock_state =3D HEX_LOCK_QUEUED; + SET_SYSCFG_FIELD(unlock_thread, SYSCFG_TLBLOCK, 1); + cpu_interrupt(cs, CPU_INTERRUPT_TLB_UNLOCK); + } + + if (qemu_loglevel_mask(CPU_LOG_MMU)) { + qemu_log_mask(CPU_LOG_MMU, "Threads after hex_tlb_unlock:\n"); + print_thread_states("\tThread"); + } + +} diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index cd6affa2f49..4df4226cbcb 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -987,7 +987,7 @@ static void hexagon_tr_init_disas_context(DisasContextB= ase *dcbase, HexagonCPU *hex_cpu =3D env_archcpu(cpu_env(cs)); uint32_t hex_flags =3D dcbase->tb->flags; =20 - ctx->mem_idx =3D MMU_USER_IDX; + ctx->mem_idx =3D FIELD_EX32(hex_flags, TB_FLAGS, MMU_INDEX); ctx->num_packets =3D 0; ctx->num_insns =3D 0; ctx->num_hvx_insns =3D 0; --=20 2.34.1