From nobody Wed Apr 8 02:52:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1773201070; cv=none; d=zohomail.com; s=zohoarc; b=b2pzpFcAY9KT6+q7o9SovfnuEFQ9goc01IA5N+bt+Jxd9+BjgfU+lM5tuILm5sPrpQrQ0dvTlxrBW+XxCUyel+gmko0MTStIpyKXQYGSqVl4tih4Rm0lW1BuZLipJHzx5qMxARARvTB48rv8IKMn8kGLXoPul+ERsgDWWCx3B4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773201070; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=sW8MW1L/qKJjbx9yOaOHfvrn+R+rAl/S8EvO1XBYITc=; b=DXkTaWF/vPk7a6Ya7fKIAqbFgMcl7o0DEthVfvtyIxZ5wZr+s/9KW3pT1JA4FpPOqXbuTZHztKuAoKLYq1MAW6B6aj5qX8KeBeMvY/mry+DHG8kNT1DdRFyCMQ7xCJ0umuLYn5oDSWCqYfnFegGNyOYSPiRMz80q2niqMSqMU98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1773201070533484.69678138758513; Tue, 10 Mar 2026 20:51:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1w0AaW-0002Ld-Q0; Tue, 10 Mar 2026 23:50:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0AaU-0002E1-8N for qemu-devel@nongnu.org; Tue, 10 Mar 2026 23:50:22 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1w0AaR-0005ng-9L for qemu-devel@nongnu.org; Tue, 10 Mar 2026 23:50:21 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 62AJ36Wp3893457 for ; Wed, 11 Mar 2026 03:50:08 GMT Received: from mail-ot1-f72.google.com (mail-ot1-f72.google.com [209.85.210.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4ctkmytyv0-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Wed, 11 Mar 2026 03:50:07 +0000 (GMT) Received: by mail-ot1-f72.google.com with SMTP id 46e09a7af769-7d496d080d8so79933156a34.0 for ; Tue, 10 Mar 2026 20:50:07 -0700 (PDT) Received: from hu-bcain-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7d76ae39b39sm946430a34.15.2026.03.10.20.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 20:50:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= sW8MW1L/qKJjbx9yOaOHfvrn+R+rAl/S8EvO1XBYITc=; b=lqkST0uIk5ZD4CnK YR2agCV8S2mpNvVSSfxluX3WFBeEva0EcDMkBvI+JXTuDOHq/my4go1PFcq1PJe2 N9OIwRMIt7knDrfbB5Cvw/eyXxubH1O0FDJHiHokU1rwNWmv4IQ9V08fffZip3aw kgZ/xGPjKDDukvJJg1I6U25qXm9HnNHMmd89huSWMucUcX4zRZ3gQKw+XyuwjfWt DbaGPsFSkYeflsJMIRgsFQefEK9kIAc4gt/DsjEaMYgN/xHRMrhPwymHAgVxgvoo /AkAgJKCVxANA/jk3pG7h0GcvvtXOkFHYeGrVady9VkwKbwatXvLD3snnK/ByWZe WVXH1A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1773201007; x=1773805807; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sW8MW1L/qKJjbx9yOaOHfvrn+R+rAl/S8EvO1XBYITc=; b=WdYibOFjMbPruSsHxb8Y3R7HdYAay8DSgB9Xz2u4aIEQdiRhV2To6CJ05VpJcDq4Rb PGUB6jdXxdGCmCtONYHkFjRxzxUTfbJnzuajDC7b4sIp7LVBzDr3S1tQ/OL8Wy7UWkDQ QPO6ULYqi60muj/jJIxCg+lKxL2g8XI++4RM4BIlgF2kyriuhY6r3u/VP8D+e9NWb+Fx 8NaMRaQmay1F7CKKlz+p7kWHJIhb9azyJT/57t2xYCTo0kFe0i4ZMsJD8GA43Ml3xk2U RmiTrjHec3tlACpcx3u9vLNYp7EtpVCV/vwZuRWXsC0jC35SdoLEu6Io/L6xcUc32Ec9 ZgSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1773201007; x=1773805807; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=sW8MW1L/qKJjbx9yOaOHfvrn+R+rAl/S8EvO1XBYITc=; b=sSC86qAn0Wosdj+IWuSvofPCbXpktZaWTSEJKTSMsb/jSooj1j42BU8ylcQCB9frHX Zxl/e2Iqu7Z3+DTU9DV/ItUq9ferWtDaGDnw6/CzTPoYkxvNcD1iT58DUd7qaVj4BhCo PYgd8M4Ias17PyKDWNi7/12YjsL4REOvn3kYA+99T3J5S36339kGSqYT6mnHHqN8NkKc LLdtsdIOG5Pqoy0wP0YnFaIReupZjsx7n63JDpFcS/ESW/eSbLVg3uSfDPR72vIKEr4N 0/mAwZrz4g9RW321bA/uufik2m/MB7Mr4QXA35SI39dQQMeYwgVGk4DTP9zzCyFqoHPL ZxkQ== X-Gm-Message-State: AOJu0Yzh6PF9I+PJnLzbKCRFAocx1uiBMulV0hlWgwkZGr3Ra+i5+MZY qn1FkjoV6za0F11HsKhTL31QdEP56FAILqiMcugjVhn5zRsCGFv7b5vXqAXkt7bquh6VC0iCDgI WA8XQuTrNFGcw6TKaTgJspvsKKh+NxDqA8MA0Gzd4X9IlkvahD+Rlx4owUrl2CH6EaQ== X-Gm-Gg: ATEYQzw6hkXkJSDAq/JC1KyrfK6TNgjk1gb5gBEy7HpDrV7YqtdRvpg8HR95a5g7faY T2XX7UWoANxrGvZtYV2HRSbB+nkJQG33iNNSk9yK4XISFgjaGuymN9j4rZ9kjABSyS9NU+/N6du 4Ovb8TdMf1SbovsBI4V9fkWZHu5hKzSQ5bUcOGBifN1qjCkS/mq4Rf3YWjBrcmWUw0Ef869jDQC f4zjCGwKbHdemoCdMZEUns1/lvEUL17AFkq6Jw+7DhB8Q48THBGc5cZ+ZWxrlkzIWur/mFpYOqD 2ODrvUPdSqKznlqH1AMdXZKR5WFjo+TDqIEUJiB5jh4zBWXu/MEzrgW+jPtm2k3YoU2Wn2IOqVc xdxkhxCkpKEtygg5227Jjbp6qXpYsZOzPHcaJ8a1gn/tghGNlS4dgcqz8A+K+Yyhy77jvcw== X-Received: by 2002:a05:6830:44ab:b0:7d7:57af:4435 with SMTP id 46e09a7af769-7d76a833e5fmr947553a34.30.1773201006752; Tue, 10 Mar 2026 20:50:06 -0700 (PDT) X-Received: by 2002:a05:6830:44ab:b0:7d7:57af:4435 with SMTP id 46e09a7af769-7d76a833e5fmr947536a34.30.1773201006271; Tue, 10 Mar 2026 20:50:06 -0700 (PDT) From: Brian Cain To: qemu-devel@nongnu.org Cc: brian.cain@oss.qualcomm.com, philmd@linaro.org, ltaylorsimpson@gmail.com, matheus.bernardino@oss.qualcomm.com, marco.liebel@oss.qualcomm.com, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng Subject: [PATCH v5 31/35] hw/hexagon: Introduce hexagon TLB device Date: Tue, 10 Mar 2026 20:49:19 -0700 Message-Id: <20260311034923.1044737-32-brian.cain@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com> References: <20260311034923.1044737-1-brian.cain@oss.qualcomm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=RYudyltv c=1 sm=1 tr=0 ts=69b0e66f cx=c_pps a=+3WqYijBVYhDct2f5Fivkw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=Yq5XynenixoA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=sP_loDDXlKxngBex9BIA:9 a=QEXdDO2ut3YA:10 a=eYe2g0i6gJ5uXG_o6N4q:22 X-Proofpoint-GUID: 2aKQeyrgiMZfsav_FxsavuGXeQJqhlxa X-Proofpoint-ORIG-GUID: 2aKQeyrgiMZfsav_FxsavuGXeQJqhlxa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzExMDAyOSBTYWx0ZWRfX+DGt23k9L8RP h9JQqmaOJJwfNBV212rilxRzQBrrb6dNb3d/DA4TWvgnd66Lz+80MJG/G56mMoCJXo1+qcl0lhi kmflaK9xYGA4oqgVbLC1ym8AYUuZi+UCc/V5q1bU5r/kudHZGhg/GPpNUYEON8cdGw0kM2QduP/ x6zLvSddbPlEpJhigMRkci6TnLLFqEnOqfh9VMsDccallq0uIPkE6oknUQ9gGefHM7hD4PIBJJN tBCo2mzasJ+ukU/1n+QwiFuAwTCy+Rot209xHKlNauEW8kcoZOkmI2UXjFQlp6B39RCdxZWVYrQ 9xPKL/6f3oMQX5PxnRx8TzHhTrJtb81Yd8Ur7KBtEopiXb5MPGyNB4C/GWVHT1a22bgVIJNyjve wNB6sKhc4YLD4xDw4d1wSSGJBc2FjZ2GwqrX9zxTP2JNNZDjqxIzgd25IGiEd8Zk67iZ2jwhOJs SdmUKGBoiroQj3tmgLQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-10_05,2026-03-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603110029 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=brian.cain@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1773201072095154100 Add the hexagon TLB QOM device model. Signed-off-by: Brian Cain Reviewed-by: Taylor Simpson --- include/hw/hexagon/hexagon_tlb.h | 45 +++ target/hexagon/cpu.h | 4 + hw/hexagon/hexagon_tlb.c | 463 +++++++++++++++++++++++++++++++ target/hexagon/cpu.c | 5 + 4 files changed, 517 insertions(+) create mode 100644 include/hw/hexagon/hexagon_tlb.h create mode 100644 hw/hexagon/hexagon_tlb.c diff --git a/include/hw/hexagon/hexagon_tlb.h b/include/hw/hexagon/hexagon_= tlb.h new file mode 100644 index 00000000000..bcb387aa24d --- /dev/null +++ b/include/hw/hexagon/hexagon_tlb.h @@ -0,0 +1,45 @@ +/* + * Hexagon TLB QOM Device + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_HEXAGON_TLB_H +#define HW_HEXAGON_TLB_H + +#include "hw/core/sysbus.h" +#include "qom/object.h" +#include "exec/hwaddr.h" +#include "exec/mmu-access-type.h" +#define TYPE_HEXAGON_TLB "hexagon-tlb" +OBJECT_DECLARE_SIMPLE_TYPE(HexagonTLBState, HEXAGON_TLB) + +struct HexagonTLBState { + SysBusDevice parent_obj; + + uint32_t num_entries; + uint64_t *entries; +}; + +uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index); +void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e); + +bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, MMUAccessType access_type, + hwaddr *PA, int *prot, uint64_t *size, + int32_t *excp, int *cause_code, int mmu_idx); + +uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, int *cause_code); + +int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry, + uint64_t index); + +void hexagon_tlb_dump(HexagonTLBState *tlb); + +bool hexagon_tlb_dump_entry(FILE *f, uint64_t entry); + +uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb); + +#endif /* HW_HEXAGON_TLB_H */ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 9eb2d1bbabe..e39e6e39fec 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -46,6 +46,7 @@ #define REG_WRITES_MAX 32 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ #define VSTORES_MAX 2 +#define MAX_TLB_ENTRIES 1024 =20 #define CPU_RESOLVING_TYPE TYPE_HEXAGON_CPU #ifndef CONFIG_USER_ONLY @@ -174,6 +175,9 @@ struct ArchCPU { bool lldb_compat; target_ulong lldb_stack_adjust; bool short_circuit; +#ifndef CONFIG_USER_ONLY + struct HexagonTLBState *tlb; +#endif }; =20 #include "cpu_bits.h" diff --git a/hw/hexagon/hexagon_tlb.c b/hw/hexagon/hexagon_tlb.c new file mode 100644 index 00000000000..90f319f56d3 --- /dev/null +++ b/hw/hexagon/hexagon_tlb.c @@ -0,0 +1,463 @@ +/* + * Hexagon TLB QOM Device + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/hexagon/hexagon_tlb.h" +#include "hw/core/qdev-properties.h" +#include "hw/core/resettable.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "target/hexagon/cpu.h" +#include "target/hexagon/cpu_bits.h" + +/* PTE (TLB entry) field extraction */ +#define GET_PTE_PPD(entry) extract64((entry), 0, 24) +#define GET_PTE_C(entry) extract64((entry), 24, 4) +#define GET_PTE_U(entry) extract64((entry), 28, 1) +#define GET_PTE_R(entry) extract64((entry), 29, 1) +#define GET_PTE_W(entry) extract64((entry), 30, 1) +#define GET_PTE_X(entry) extract64((entry), 31, 1) +#define GET_PTE_VPN(entry) extract64((entry), 32, 20) +#define GET_PTE_ASID(entry) extract64((entry), 52, 7) +#define GET_PTE_ATR0(entry) extract64((entry), 59, 1) +#define GET_PTE_ATR1(entry) extract64((entry), 60, 1) +#define GET_PTE_PA35(entry) extract64((entry), 61, 1) +#define GET_PTE_G(entry) extract64((entry), 62, 1) +#define GET_PTE_V(entry) extract64((entry), 63, 1) + +/* PPD (physical page descriptor) */ +static inline uint64_t GET_PPD(uint64_t entry) +{ + return GET_PTE_PPD(entry) | (GET_PTE_PA35(entry) << 24); +} + +#define NO_ASID (1 << 8) + +typedef enum { + PGSIZE_4K, + PGSIZE_16K, + PGSIZE_64K, + PGSIZE_256K, + PGSIZE_1M, + PGSIZE_4M, + PGSIZE_16M, + PGSIZE_64M, + PGSIZE_256M, + PGSIZE_1G, + NUM_PGSIZE_TYPES +} tlb_pgsize_t; + +static const char *pgsize_str[NUM_PGSIZE_TYPES] =3D { + "4K", + "16K", + "64K", + "256K", + "1M", + "4M", + "16M", + "64M", + "256M", + "1G", +}; + +#define INVALID_MASK 0xffffffffLL + +static const uint64_t encmask_2_mask[] =3D { + 0x0fffLL, /* 4k, 0000 */ + 0x3fffLL, /* 16k, 0001 */ + 0xffffLL, /* 64k, 0010 */ + 0x3ffffLL, /* 256k, 0011 */ + 0xfffffLL, /* 1m, 0100 */ + 0x3fffffLL, /* 4m, 0101 */ + 0xffffffLL, /* 16m, 0110 */ + 0x3ffffffLL, /* 64m, 0111 */ + 0xfffffffLL, /* 256m, 1000 */ + 0x3fffffffLL, /* 1g, 1001 */ + INVALID_MASK, /* RSVD, 0111 */ +}; + +static inline tlb_pgsize_t hex_tlb_pgsize_type(uint64_t entry) +{ + if (entry =3D=3D 0) { + qemu_log_mask(CPU_LOG_MMU, "%s: Supplied TLB entry was 0!\n", + __func__); + return 0; + } + tlb_pgsize_t size =3D ctz64(entry); + g_assert(size < NUM_PGSIZE_TYPES); + return size; +} + +static inline uint64_t hex_tlb_page_size_bytes(uint64_t entry) +{ + return 1ull << (TARGET_PAGE_BITS + 2 * hex_tlb_pgsize_type(entry)); +} + +static inline uint64_t hex_tlb_phys_page_num(uint64_t entry) +{ + uint32_t ppd =3D GET_PPD(entry); + return ppd >> 1; +} + +static inline uint64_t hex_tlb_phys_addr(uint64_t entry) +{ + uint64_t pagemask =3D encmask_2_mask[hex_tlb_pgsize_type(entry)]; + uint64_t pagenum =3D hex_tlb_phys_page_num(entry); + uint64_t PA =3D (pagenum << TARGET_PAGE_BITS) & (~pagemask); + return PA; +} + +static inline uint64_t hex_tlb_virt_addr(uint64_t entry) +{ + return (uint64_t)GET_PTE_VPN(entry) << TARGET_PAGE_BITS; +} + +bool hexagon_tlb_dump_entry(FILE *f, uint64_t entry) +{ + if (GET_PTE_V(entry)) { + fprintf(f, "0x%016" PRIx64 ": ", entry); + uint64_t PA =3D hex_tlb_phys_addr(entry); + uint64_t VA =3D hex_tlb_virt_addr(entry); + fprintf(f, "V:%" PRId64 " G:%" PRId64 + " A1:%" PRId64 " A0:%" PRId64, + GET_PTE_V(entry), + GET_PTE_G(entry), + GET_PTE_ATR1(entry), + GET_PTE_ATR0(entry)); + fprintf(f, " ASID:0x%02" PRIx64 " VA:0x%08" PRIx64, + GET_PTE_ASID(entry), VA); + fprintf(f, + " X:%" PRId64 " W:%" PRId64 " R:%" PRId64 + " U:%" PRId64 " C:%" PRId64, + GET_PTE_X(entry), + GET_PTE_W(entry), + GET_PTE_R(entry), + GET_PTE_U(entry), + GET_PTE_C(entry)); + fprintf(f, " PA:0x%09" PRIx64 " SZ:%s (0x%" PRIx64 ")", PA, + pgsize_str[hex_tlb_pgsize_type(entry)], + hex_tlb_page_size_bytes(entry)); + fprintf(f, "\n"); + return true; + } + + /* Not valid */ + return false; +} + +static inline bool hex_tlb_entry_match_noperm(uint64_t entry, uint32_t asi= d, + uint64_t VA) +{ + if (GET_PTE_V(entry)) { + if (GET_PTE_G(entry)) { + /* Global entry - ignore ASID */ + } else if (asid !=3D NO_ASID) { + uint32_t tlb_asid =3D GET_PTE_ASID(entry); + if (tlb_asid !=3D asid) { + return false; + } + } + + uint64_t page_size =3D hex_tlb_page_size_bytes(entry); + uint64_t page_start =3D + ROUND_DOWN(hex_tlb_virt_addr(entry), page_size); + if (page_start <=3D VA && VA < page_start + page_size) { + return true; + } + } + return false; +} + +static inline void hex_tlb_entry_get_perm(uint64_t entry, + MMUAccessType access_type, + int mmu_idx, int *prot, + int32_t *excp, int *cause_code) +{ + bool perm_x =3D GET_PTE_X(entry); + bool perm_w =3D GET_PTE_W(entry); + bool perm_r =3D GET_PTE_R(entry); + bool perm_u =3D GET_PTE_U(entry); + bool user_idx =3D mmu_idx =3D=3D MMU_USER_IDX; + + if (mmu_idx =3D=3D MMU_KERNEL_IDX) { + *prot =3D PAGE_VALID | PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return; + } + + *prot =3D PAGE_VALID; + switch (access_type) { + case MMU_INST_FETCH: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_UPAGE; + } else if (!perm_x) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_FETCH_NO_XPAGE; + } + break; + case MMU_DATA_LOAD: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UREAD; + } else if (!perm_r) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_READ; + } + break; + case MMU_DATA_STORE: + if (user_idx && !perm_u) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_UWRITE; + } else if (!perm_w) { + *excp =3D HEX_EVENT_PRECISE; + *cause_code =3D HEX_CAUSE_PRIV_NO_WRITE; + } + break; + } + + if (!user_idx || perm_u) { + if (perm_x) { + *prot |=3D PAGE_EXEC; + } + if (perm_r) { + *prot |=3D PAGE_READ; + } + if (perm_w) { + *prot |=3D PAGE_WRITE; + } + } +} + +static inline bool hex_tlb_entry_match(uint64_t entry, uint8_t asid, + uint32_t VA, + MMUAccessType access_type, hwaddr *= PA, + int *prot, uint64_t *size, + int32_t *excp, int *cause_code, + int mmu_idx) +{ + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + hex_tlb_entry_get_perm(entry, access_type, mmu_idx, prot, excp, + cause_code); + *PA =3D hex_tlb_phys_addr(entry); + *size =3D hex_tlb_page_size_bytes(entry); + return true; + } + return false; +} + +static bool hex_tlb_is_match(uint64_t entry1, uint64_t entry2, + bool consider_gbit) +{ + bool valid1 =3D GET_PTE_V(entry1); + bool valid2 =3D GET_PTE_V(entry2); + uint64_t size1 =3D hex_tlb_page_size_bytes(entry1); + uint64_t vaddr1 =3D ROUND_DOWN(hex_tlb_virt_addr(entry1), size1); + uint64_t size2 =3D hex_tlb_page_size_bytes(entry2); + uint64_t vaddr2 =3D ROUND_DOWN(hex_tlb_virt_addr(entry2), size2); + int asid1 =3D GET_PTE_ASID(entry1); + int asid2 =3D GET_PTE_ASID(entry2); + bool gbit1 =3D GET_PTE_G(entry1); + bool gbit2 =3D GET_PTE_G(entry2); + + if (!valid1 || !valid2) { + return false; + } + + if (((vaddr1 <=3D vaddr2) && (vaddr2 < (vaddr1 + size1))) || + ((vaddr2 <=3D vaddr1) && (vaddr1 < (vaddr2 + size2)))) { + if (asid1 =3D=3D asid2) { + return true; + } + if ((consider_gbit && gbit1) || gbit2) { + return true; + } + } + return false; +} + +/* Public API */ + +uint64_t hexagon_tlb_read(HexagonTLBState *tlb, uint32_t index) +{ + g_assert(index < tlb->num_entries); + return tlb->entries[index]; +} + +void hexagon_tlb_write(HexagonTLBState *tlb, uint32_t index, uint64_t valu= e) +{ + g_assert(index < tlb->num_entries); + tlb->entries[index] =3D value; +} + +bool hexagon_tlb_find_match(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, MMUAccessType access_type, + hwaddr *PA, int *prot, uint64_t *size, + int32_t *excp, int *cause_code, int mmu_idx) +{ + *PA =3D 0; + *prot =3D 0; + *size =3D 0; + *excp =3D 0; + *cause_code =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_entry_match(tlb->entries[i], asid, VA, access_type, + PA, prot, size, excp, cause_code, mmu_idx)= ) { + return true; + } + } + return false; +} + +uint32_t hexagon_tlb_lookup(HexagonTLBState *tlb, uint32_t asid, + uint32_t VA, int *cause_code) +{ + uint32_t not_found =3D 0x80000000; + uint32_t idx =3D not_found; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + uint64_t entry =3D tlb->entries[i]; + if (hex_tlb_entry_match_noperm(entry, asid, VA)) { + if (idx !=3D not_found) { + *cause_code =3D HEX_CAUSE_IMPRECISE_MULTI_TLB_MATCH; + break; + } + idx =3D i; + } + } + + if (idx =3D=3D not_found) { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> NOT FOUND\n= ", + __func__, asid, VA); + } else { + qemu_log_mask(CPU_LOG_MMU, + "%s: 0x%" PRIx32 ", 0x%08" PRIx32 " =3D> %d\n", + __func__, asid, VA, idx); + } + + return idx; +} + +/* + * Return codes: + * 0 or positive index of match + * -1 multiple matches + * -2 no match + */ +int hexagon_tlb_check_overlap(HexagonTLBState *tlb, uint64_t entry, + uint64_t index) +{ + int matches =3D 0; + int last_match =3D 0; + + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + if (hex_tlb_is_match(entry, tlb->entries[i], false)) { + matches++; + last_match =3D i; + } + } + + if (matches =3D=3D 1) { + return last_match; + } + if (matches =3D=3D 0) { + return -2; + } + return -1; +} + +void hexagon_tlb_dump(HexagonTLBState *tlb) +{ + for (uint32_t i =3D 0; i < tlb->num_entries; i++) { + hexagon_tlb_dump_entry(stdout, tlb->entries[i]); + } +} + +uint32_t hexagon_tlb_get_num_entries(HexagonTLBState *tlb) +{ + return tlb->num_entries; +} + +/* QOM lifecycle */ + +static void hexagon_tlb_init(Object *obj) +{ +} + +static void hexagon_tlb_realize(DeviceState *dev, Error **errp) +{ + HexagonTLBState *s =3D HEXAGON_TLB(dev); + + if (s->num_entries =3D=3D 0 || s->num_entries > MAX_TLB_ENTRIES) { + error_setg(errp, "Invalid TLB num-entries: %" PRIu32, + s->num_entries); + return; + } + s->entries =3D g_new0(uint64_t, s->num_entries); +} + +static void hexagon_tlb_finalize(Object *obj) +{ + HexagonTLBState *s =3D HEXAGON_TLB(obj); + g_free(s->entries); + s->entries =3D NULL; +} + +static void hexagon_tlb_reset_hold(Object *obj, ResetType type) +{ + HexagonTLBState *s =3D HEXAGON_TLB(obj); + if (s->entries) { + memset(s->entries, 0, sizeof(uint64_t) * s->num_entries); + } +} + +static const VMStateDescription vmstate_hexagon_tlb =3D { + .name =3D "hexagon-tlb", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32(num_entries, HexagonTLBState), + VMSTATE_VARRAY_UINT32_ALLOC(entries, HexagonTLBState, num_entries, + 0, vmstate_info_uint64, uint64_t), + VMSTATE_END_OF_LIST() + }, +}; + +static const Property hexagon_tlb_properties[] =3D { + DEFINE_PROP_UINT32("num-entries", HexagonTLBState, num_entries, + MAX_TLB_ENTRIES), +}; + +static void hexagon_tlb_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + dc->realize =3D hexagon_tlb_realize; + rc->phases.hold =3D hexagon_tlb_reset_hold; + dc->vmsd =3D &vmstate_hexagon_tlb; + dc->user_creatable =3D false; + device_class_set_props(dc, hexagon_tlb_properties); +} + +static const TypeInfo hexagon_tlb_info =3D { + .name =3D TYPE_HEXAGON_TLB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(HexagonTLBState), + .instance_init =3D hexagon_tlb_init, + .instance_finalize =3D hexagon_tlb_finalize, + .class_init =3D hexagon_tlb_class_init, +}; + +static void hexagon_tlb_register_types(void) +{ + type_register_static(&hexagon_tlb_info); +} + +type_init(hexagon_tlb_register_types) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b1317f83ef4..32d158684a0 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -23,6 +23,7 @@ #include "qapi/error.h" #include "hw/core/qdev-properties.h" #include "fpu/softfloat-helpers.h" +#include "hw/hexagon/hexagon_tlb.h" #include "tcg/tcg.h" #include "exec/gdbstub.h" #include "accel/tcg/cpu-ops.h" @@ -50,6 +51,10 @@ static ObjectClass *hexagon_cpu_class_by_name(const char= *cpu_model) } =20 static const Property hexagon_cpu_properties[] =3D { +#if !defined(CONFIG_USER_ONLY) + DEFINE_PROP_LINK("tlb", HexagonCPU, tlb, TYPE_HEXAGON_TLB, + HexagonTLBState *), +#endif DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false), DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjus= t, 0, qdev_prop_uint32, target_ulong), --=20 2.34.1