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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=136.143.188.54; envelope-from=anirudh@anirudhrb.com; helo=sender4-of-o54.zoho.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity anirudh@anirudhrb.com) X-ZM-MESSAGEID: 1773242790710154100 From: Aastha Rawat Enable access_vp_regs feature for regs. In arm64, this feature bit allows the guest to set VP registers using hypercall. This wasn't required for x86 because such registers are set using wrmsr instead of hypercall. Signed-off-by: Aastha Rawat --- accel/mshv/mshv-all.c | 1 + include/hw/hyperv/hvhdk.h | 87 +++++++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 85 insertions(+), 3 deletions(-) diff --git a/accel/mshv/mshv-all.c b/accel/mshv/mshv-all.c index d63b3a53bf..563599ef6a 100644 --- a/accel/mshv/mshv-all.c +++ b/accel/mshv/mshv-all.c @@ -199,6 +199,7 @@ static int set_synthetic_proc_features(int vm_fd) features.tb_flush_hypercalls =3D 1; features.synthetic_cluster_ipi =3D 1; features.direct_synthetic_timers =3D 1; + features.access_vp_regs =3D 1; =20 mshv_arch_amend_proc_features(&features); =20 diff --git a/include/hw/hyperv/hvhdk.h b/include/hw/hyperv/hvhdk.h index 2e1ef80972..38af01f8ea 100644 --- a/include/hw/hyperv/hvhdk.h +++ b/include/hw/hyperv/hvhdk.h @@ -94,11 +94,15 @@ union hv_partition_synthetic_processor_features { */ uint64_t access_partition_reference_tsc:1; =20 - /* - * Partition has access to the guest idle reg. Corresponds to +#if defined(__x86_64__) + + /* Partition has access to the guest idle reg. Corresponds to * access_guest_idle_reg privilege. */ uint64_t access_guest_idle_reg:1; +#else + uint64_t reserved_z10:1; +#endif =20 /* * Partition has access to frequency regs. corresponds to @@ -110,11 +114,16 @@ union hv_partition_synthetic_processor_features { uint64_t reserved_z13:1; /* Reserved for access_root_scheduler_reg= */ uint64_t reserved_z14:1; /* Reserved for access_tsc_invariant_cont= rols */ =20 +#if defined(__x86_64__) + /* * Extended GVA ranges for HvCallFlushVirtualAddressList hypercall. * Corresponds to privilege. */ uint64_t enable_extended_gva_ranges_for_flush_virtual_address_list= :1; +#else + uint64_t reserved_z15:1; +#endif =20 uint64_t reserved_z16:1; /* Reserved for access_vsm. */ uint64_t reserved_z17:1; /* Reserved for access_vp_registers. */ @@ -161,13 +170,85 @@ union hv_partition_synthetic_processor_features { /* HvCallRetargetDeviceInterrupt is supported. */ uint64_t retarget_device_interrupt:1; =20 +#if defined(__x86_64__) /* HvCallRestorePartitionTime is supported. */ uint64_t restore_time:1; =20 /* EnlightenedVmcs nested enlightenment is supported. */ uint64_t enlightened_vmcs:1; =20 - uint64_t reserved:30; + uint64_t nested_debug_ctl:1; + uint64_t synthetic_time_unhalted_timer:1; + uint64_t idle_spec_ctrl:1; + +#else + uint64_t reserved_z31:1; + uint64_t reserved_z32:1; + uint64_t reserved_z33:1; + uint64_t reserved_z34:1; + uint64_t reserved_z35:1; +#endif + +#if defined(__aarch64__) + /* Register intercepts supported in V1. As more registers are supp= orted in future + * releases, new bits will be added here to prevent migration betw= een incompatible hosts. + * + * List of registers supported in V1: + * 1. TPIDRRO_EL0 + * 2. TPIDR_EL1 + * 3. SCTLR_EL1 - Supports write intercept mask. + * 4. VBAR_EL1 + * 5. TCR_EL1 - Supports write intercept mask. + * 6. MAIR_EL1 - Supports write intercept mask. + * 7. CPACR_EL1 - Supports write intercept mask. + * 8. CONTEXTIDR_EL1 + * 9. PAuth keys (total 10 registers) + * 10. HvArm64RegisterSyntheticException + */ + uint64_t register_intercepts_v1:1; +#else + uint64_t reserved_z36:1; +#endif + + /* HvCallWakeVps is supported */ + uint64_t wake_vps:1; + + /* HvCallGet/SetVpRegisters is supported. + * Corresponds to AccessVpRegisters privilege. + * This feature only affects exo partitions. + */ + uint64_t access_vp_regs:1; + +#if defined(__aarch64__) + /* HvCallSyncContext/Ex is supported. */ + uint64_t sync_context:1; +#else + uint64_t reserved_z39:1; +#endif /* __aarch64__ */ + + /* Management VTL synic support is allowed. + * Corresponds to the ManagementVtlSynicSupport privilege. + */ + uint64_t management_vtl_synic_support:1; + +#if defined(__x86_64__) + /* Hypervisor supports guest mechanism to signal pending interrupt= s to paravisor. */ + uint64_t proxy_interrupt_doorbell_support:1; +#else + uint64_t reserved_z41:1; +#endif + +#if defined(__aarch64__) + /* InterceptSystemResetAvailable is exposed. */ + uint64_t intercept_system_reset:1; +#else + uint64_t reserved_z42:1; +#endif + + /* Hypercalls for host MMIO operations are available. */ + uint64_t mmio_hypercalls:1; + + uint64_t reserved:20; }; }; =20 --=20 2.43.0