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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=136.143.188.54; envelope-from=anirudh@anirudhrb.com; helo=sender4-of-o54.zoho.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity anirudh@anirudhrb.com) X-ZM-MESSAGEID: 1773242792788154100 From: Aastha Rawat Add support for reading and writing ARM64 CPU registers in the MSHV accelerator. This includes functions to set and get registers, initialize and destroy VCPU state, and manage register state synchronization between QEMU and hypervisor. Signed-off-by: Aastha Rawat --- include/hw/hyperv/hvgdk_mini.h | 42 +++++++++++++ target/arm/mshv/mshv-all.c | 138 +++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 180 insertions(+) diff --git a/include/hw/hyperv/hvgdk_mini.h b/include/hw/hyperv/hvgdk_mini.h index cb52cc9de2..dfe94050f4 100644 --- a/include/hw/hyperv/hvgdk_mini.h +++ b/include/hw/hyperv/hvgdk_mini.h @@ -13,6 +13,46 @@ typedef enum hv_register_name { /* Pending Interruption Register */ HV_REGISTER_PENDING_INTERRUPTION =3D 0x00010002, =20 +#if defined(__aarch64__) + HV_ARM64_REGISTER_XZR =3D 0x0002FFFE, + HV_ARM64_REGISTER_X0 =3D 0x00020000, + HV_ARM64_REGISTER_X1 =3D 0x00020001, + HV_ARM64_REGISTER_X2 =3D 0x00020002, + HV_ARM64_REGISTER_X3 =3D 0x00020003, + HV_ARM64_REGISTER_X4 =3D 0x00020004, + HV_ARM64_REGISTER_X5 =3D 0x00020005, + HV_ARM64_REGISTER_X6 =3D 0x00020006, + HV_ARM64_REGISTER_X7 =3D 0x00020007, + HV_ARM64_REGISTER_X8 =3D 0x00020008, + HV_ARM64_REGISTER_X9 =3D 0x00020009, + HV_ARM64_REGISTER_X10 =3D 0x0002000A, + HV_ARM64_REGISTER_X11 =3D 0x0002000B, + HV_ARM64_REGISTER_X12 =3D 0x0002000C, + HV_ARM64_REGISTER_X13 =3D 0x0002000D, + HV_ARM64_REGISTER_X14 =3D 0x0002000E, + HV_ARM64_REGISTER_X15 =3D 0x0002000F, + HV_ARM64_REGISTER_X16 =3D 0x00020010, + HV_ARM64_REGISTER_X17 =3D 0x00020011, + HV_ARM64_REGISTER_X18 =3D 0x00020012, + HV_ARM64_REGISTER_X19 =3D 0x00020013, + HV_ARM64_REGISTER_X20 =3D 0x00020014, + HV_ARM64_REGISTER_X21 =3D 0x00020015, + HV_ARM64_REGISTER_X22 =3D 0x00020016, + HV_ARM64_REGISTER_X23 =3D 0x00020017, + HV_ARM64_REGISTER_X24 =3D 0x00020018, + HV_ARM64_REGISTER_X25 =3D 0x00020019, + HV_ARM64_REGISTER_X26 =3D 0x0002001A, + HV_ARM64_REGISTER_X27 =3D 0x0002001B, + HV_ARM64_REGISTER_X28 =3D 0x0002001C, + HV_ARM64_REGISTER_FP =3D 0x0002001D, + HV_ARM64_REGISTER_LR =3D 0x0002001E, + HV_ARM64_REGISTER_PC =3D 0x00020022, + + /* AArch64 System Register Descriptions: General system control regist= ers */ + HV_ARM64_REGISTER_MIDR_EL1 =3D 0x00040051, + HV_ARM64_REGISTER_MPIDR_EL1 =3D 0x00040001, + +#elif defined(__x86_64__) /* X64 User-Mode Registers */ HV_X64_REGISTER_RAX =3D 0x00020000, HV_X64_REGISTER_RCX =3D 0x00020001, @@ -157,6 +197,8 @@ typedef enum hv_register_name { /* Other MSRs */ HV_X64_REGISTER_MSR_IA32_MISC_ENABLE =3D 0x000800A0, =20 +#endif + /* Misc */ HV_REGISTER_GUEST_OS_ID =3D 0x00090002, HV_REGISTER_REFERENCE_TSC =3D 0x00090017, diff --git a/target/arm/mshv/mshv-all.c b/target/arm/mshv/mshv-all.c index 1c82e2c593..ad9cb267a8 100644 --- a/target/arm/mshv/mshv-all.c +++ b/target/arm/mshv/mshv-all.c @@ -9,16 +9,146 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ =20 + +#include "qemu/osdep.h" +#include + +#include "qemu/error-report.h" +#include "qemu/memalign.h" + +#include "system/cpus.h" +#include "target/arm/cpu.h" + #include "system/mshv.h" #include "system/mshv_int.h" +#include "hw/hyperv/hvgdk_mini.h" + +static enum hv_register_name STANDARD_REGISTER_NAMES[32] =3D { + HV_ARM64_REGISTER_X0, + HV_ARM64_REGISTER_X1, + HV_ARM64_REGISTER_X2, + HV_ARM64_REGISTER_X3, + HV_ARM64_REGISTER_X4, + HV_ARM64_REGISTER_X5, + HV_ARM64_REGISTER_X6, + HV_ARM64_REGISTER_X7, + HV_ARM64_REGISTER_X8, + HV_ARM64_REGISTER_X9, + HV_ARM64_REGISTER_X10, + HV_ARM64_REGISTER_X11, + HV_ARM64_REGISTER_X12, + HV_ARM64_REGISTER_X13, + HV_ARM64_REGISTER_X14, + HV_ARM64_REGISTER_X15, + HV_ARM64_REGISTER_X16, + HV_ARM64_REGISTER_X17, + HV_ARM64_REGISTER_X18, + HV_ARM64_REGISTER_X19, + HV_ARM64_REGISTER_X20, + HV_ARM64_REGISTER_X21, + HV_ARM64_REGISTER_X22, + HV_ARM64_REGISTER_X23, + HV_ARM64_REGISTER_X24, + HV_ARM64_REGISTER_X25, + HV_ARM64_REGISTER_X26, + HV_ARM64_REGISTER_X27, + HV_ARM64_REGISTER_X28, + HV_ARM64_REGISTER_FP, + HV_ARM64_REGISTER_LR, + HV_ARM64_REGISTER_PC, +}; + +static int set_standard_regs(const CPUState *cpu) +{ + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + struct hv_register_assoc *assocs; + int ret; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + + assocs =3D g_new0(hv_register_assoc, n_regs); + + for (size_t i =3D 0; i < n_regs - 1; i++) { + assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; + assocs[i].value.reg64 =3D env->xregs[i]; + } + + /* Last register is the program counter */ + assocs[n_regs - 1].name =3D STANDARD_REGISTER_NAMES[n_regs - 1]; + assocs[n_regs - 1].value.reg64 =3D env->pc; + + ret =3D mshv_set_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to set standard registers"); + g_free(assocs); + return -1; + } + + g_free(assocs); + + return 0; +} + +static void populate_standard_regs(const hv_register_assoc *assocs, + CPUARMState *env) +{ + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + + for (size_t i =3D 0; i < n_regs - 1; i++) { + env->xregs[i] =3D assocs[i].value.reg64; + } + + /* Last register is the program counter */ + env->pc =3D assocs[n_regs - 1].value.reg64; +} =20 int mshv_load_regs(CPUState *cpu) { + int ret; + + ret =3D mshv_get_standard_regs(cpu); + if (ret < 0) { + error_report("Failed to load standard registers"); + return -1; + } + + return 0; +} + +int mshv_get_standard_regs(CPUState *cpu) +{ + size_t n_regs =3D ARRAY_SIZE(STANDARD_REGISTER_NAMES); + struct hv_register_assoc *assocs; + int ret; + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + + assocs =3D g_new0(hv_register_assoc, n_regs); + for (size_t i =3D 0; i < n_regs; i++) { + assocs[i].name =3D STANDARD_REGISTER_NAMES[i]; + } + ret =3D mshv_get_generic_regs(cpu, assocs, n_regs); + if (ret < 0) { + error_report("failed to get standard registers"); + g_free(assocs); + return -1; + } + + populate_standard_regs(assocs, env); + + g_free(assocs); return 0; } =20 int mshv_arch_put_registers(const CPUState *cpu) { + int ret; + + ret =3D set_standard_regs(cpu); + if (ret < 0) { + return ret; + } + return 0; } =20 @@ -29,12 +159,20 @@ int mshv_run_vcpu(int vm_fd, CPUState *cpu, hv_message= *msg, MshvVmExit *exit) =20 void mshv_arch_init_vcpu(CPUState *cpu) { + AccelCPUState *state =3D cpu->accel; =20 + mshv_setup_hvcall_args(state); } =20 void mshv_arch_destroy_vcpu(CPUState *cpu) { + AccelCPUState *state =3D cpu->accel; + + if (state->hvcall_args.base) { + qemu_vfree(state->hvcall_args.base); + } =20 + state->hvcall_args =3D (MshvHvCallArgs){0}; } =20 void mshv_init_mmio_emu(void) --=20 2.43.0