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a="78048244" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="78048244" X-CSE-ConnectionGUID: kGA9/KI7SUG57tAPSes/Eg== X-CSE-MsgGUID: ofk3Bqi2TlmvsIdN9JzMKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="217647998" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu , Zhijun Zeng , Chao Peng Subject: [PATCH 5/5] i386/cpu: Enable CPUID 0x1f & cache model for ClearwaterForest Date: Tue, 10 Mar 2026 22:08:19 +0800 Message-Id: <20260310140819.1563084-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150175481158500 Content-Type: text/plain; charset="utf-8" ClearwaterForest has CPUID 0x1f by default, so force enabling this leaf for it (ClearwaterForect-v3). And add the cache model to ClearwaterForest (v3) to better emulate its environment. The cache model is based on ClearwaterForest-AP (Advanced Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x80 (128) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 128 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7 (7) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x1000 (4096) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 4096 (size synth) =3D 4194304 (4 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x3ff (1023) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x84000 (540672) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 540672 (size synth) =3D 553648128 (528 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Zhijun Zeng Suggested-by: Chao Peng Signed-off-by: Zhao Liu --- target/i386/cpu.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a3c8f523e85b..4b6aed770a15 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3318,6 +3318,97 @@ static const CPUCaches xeon_srf_cache_info =3D { }, }; =20 +static const CPUCaches xeon_cwf_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 128, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 4096, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 4 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_MODULE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 540672, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 528 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches yongfeng_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -5963,9 +6054,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with its-no", + .note =3D "with its-no, cwf-ap cache model and 0x1f leaf", + .cache_info =3D &xeon_cwf_cache_info, .props =3D (PropValue[]) { { "its-no", "on" }, + { "x-force-cpuid-0x1f", "on" }, { /* end of list */ }, } }, --=20 2.34.1