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Tue, 10 Mar 2026 09:42:27 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 06:42:20 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 10 Mar 2026 06:42:19 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773150144; x=1804686144; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F1OQS3PY94wOxpRKqt48XHCF9VcpDNaMAeV19dQvbPk=; b=T8tolifRphVC0sSlFhNLi0DnA4gbapM5YeGJrAUsIKKrsjDQMr1uu4Zf 12OpsJurNqLCMtVzghoHA1HrtQ7w0/bE5Njjtyi7vDjvOJnW04ZZPvF0T vbyi6vi+msVKuWkCXDuJMzoWdCaBFID5EuAzBjYUwFL0kRHDzYzwp3Nup 4nO7foRk/7le3wptCHzJa8WStzQBXtqbR38Ow8l6d4aHC0i3B3T5brN0V AsTCND24iITa45kcnKqH+lVQYkaB/oPNkGs88BLPUImLvcHJFVQqUq1q2 4tUbeg4dRsD3Ism2uoiXrFFUnh2v5kWY2NF0ckaQ74eibP2cUzVUsvaxF g==; X-CSE-ConnectionGUID: sQCG1UnCQj+TfqszzOYiHA== X-CSE-MsgGUID: HIebVvIuSPenm5r73C9QiA== X-IronPort-AV: E=McAfee;i="6800,10657,11725"; a="78048233" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="78048233" X-CSE-ConnectionGUID: T4VGanmVQ1Swh+cpIQBb2g== X-CSE-MsgGUID: bZZU7lDNRp+bj5t/bSWisA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="217647968" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 1/5] i386/cpu: Rename AMX mirror cpuid macros with _ALIAS suffix Date: Tue, 10 Mar 2026 22:08:15 +0800 Message-Id: <20260310140819.1563084-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150221656154100 Content-Type: text/plain; charset="utf-8" For the similar case - CPUID_EXT2_AMD_ALIASES, the term "alias" has already been used. Therefore, reintroducing the new term "mirror" is likely to cause confusion. Rename the relevant CPUID macros of AMX with _ALIAS suffix, aligning with KVM's naming convention. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 6 +++--- target/i386/cpu.h | 16 ++++++++-------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c77addd2c25a..953770db9c9a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5550,9 +5550,9 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, .features[FEAT_1E_1_EAX] =3D - CPUID_1E_1_EAX_AMX_INT8_MIRROR | CPUID_1E_1_EAX_AMX_BF16_MIRRO= R | - CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR | - CPUID_1E_1_EAX_AMX_FP16_MIRROR | CPUID_1E_1_EAX_AMX_FP8 | + CPUID_1E_1_EAX_AMX_INT8_ALIAS | CPUID_1E_1_EAX_AMX_BF16_ALIAS | + CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS | + CPUID_1E_1_EAX_AMX_FP16_ALIAS | CPUID_1E_1_EAX_AMX_FP8 | CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 | CPUID_1E_1_EAX_AMX_MOVRS, .features[FEAT_29_0_EBX] =3D CPUID_29_0_EBX_APX_NCI_NDD_NF, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2b70d56e9b03..a34c874839ad 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1098,14 +1098,14 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU = *cpu, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 -/* AMX_INT8 instruction (mirror of CPUID_7_0_EDX_AMX_INT8) */ -#define CPUID_1E_1_EAX_AMX_INT8_MIRROR (1U << 0) -/* AMX_BF16 instruction (mirror of CPUID_7_0_EDX_AMX_BF16) */ -#define CPUID_1E_1_EAX_AMX_BF16_MIRROR (1U << 1) -/* AMX_COMPLEX instruction (mirror of CPUID_7_1_EDX_AMX_COMPLEX) */ -#define CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR (1U << 2) -/* AMX_FP16 instruction (mirror of CPUID_7_1_EAX_AMX_FP16) */ -#define CPUID_1E_1_EAX_AMX_FP16_MIRROR (1U << 3) +/* AMX_INT8 instruction (alias of CPUID_7_0_EDX_AMX_INT8) */ +#define CPUID_1E_1_EAX_AMX_INT8_ALIAS (1U << 0) +/* AMX_BF16 instruction (alias of CPUID_7_0_EDX_AMX_BF16) */ +#define CPUID_1E_1_EAX_AMX_BF16_ALIAS (1U << 1) +/* AMX_COMPLEX instruction (alias of CPUID_7_1_EDX_AMX_COMPLEX) */ +#define CPUID_1E_1_EAX_AMX_COMPLEX_ALIAS (1U << 2) +/* AMX_FP16 instruction (alias of CPUID_7_1_EAX_AMX_FP16) */ +#define CPUID_1E_1_EAX_AMX_FP16_ALIAS (1U << 3) /* AMX_FP8 instruction */ #define CPUID_1E_1_EAX_AMX_FP8 (1U << 4) /* AMX_TF32 instruction */ --=20 2.34.1 From nobody Sat Apr 11 20:10:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1773150225; cv=none; d=zohomail.com; s=zohoarc; b=WhdKl0O0zuVY8oVzv5b0daSobhoJckLf7iTG1kyzued8SAUJ0s8HuNc+M+79ZkhXVPFyNxIiAH5OMeEIQlwz7WYaR8sNwK8VAxjDhx3Nz3+8F3jlzWkrmPpQKCq1rXPtDzqBmQFtxTDUYa/YqEtko0H7eC3aKw03ZqvJD3Yyw9E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1773150225; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gu2KNWqBSvw6LUHKNf8mCjJLaEYL20Vmq7L/k3dCruw=; b=E8DJPzGWM9Z5kS0s7mEsbca0HdZcbJf3K/PHC8y15IwpvbHeHtTznhN4oy6YK46XQADGyIEL6ZyggXLpiEasOukPTevT2rnKObcrHto0bCHUaAFPI0c001zjc7lplRL3d7CZdgx1khG5P03zP/+JcuDmTvCJT6xLkDJXAEmLlRM= ARC-Authentication-Results: i=1; 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Tue, 10 Mar 2026 09:42:28 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 06:42:21 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 10 Mar 2026 06:42:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773150146; x=1804686146; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=D0hw7OIpiW/NE4xd5uMdafmsbvzsIf/gcO9TbnVEeh8=; b=VvdtHSTGpOjota/0drd+Fhvc5qUQlY9+j3NYVbL1ca+s5vMYVwMb8zan jembudUl/rXhigIbIIMG5Bi7dIgocIJQHUUcbu7LiH2xZL/wG21Hnmyag Dqawzr1Fzsa6WBx1dqAIMt2VHJz0KbV6wOMHSa7wZ61YhNqgBIfYZ8bdS ExcO55BPUmGvKgQpyG89MUNmEnDpF2bJydQS9TlZxg3oXqC8NAcCEg6ky t6gS32vze12w6jbcapj3UbdnjCFSkTsjKb6fnKBQyWglBEinEXmT4cuWp bpKy1O7PLdka3reIVjW5mPTkyoQVmJPqvmNVkrlrM7wjNtUpayP44towG w==; X-CSE-ConnectionGUID: VYyCoWRlTxGkcmy9NNwncg== X-CSE-MsgGUID: RLMsDV4FTHqsDh0zSZ02zQ== X-IronPort-AV: E=McAfee;i="6800,10657,11725"; a="78048235" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="78048235" X-CSE-ConnectionGUID: PePB4s93S5KOulPFLpye5g== X-CSE-MsgGUID: Pb31thVoSQuAoswSMyFGzg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="217647971" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 2/5] i386/cpu: Rename AMX mirror feature words with -alias suffix Date: Tue, 10 Mar 2026 22:08:16 +0800 Message-Id: <20260310140819.1563084-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150226863158500 Content-Type: text/plain; charset="utf-8" The commit 956b8f0fc38a ("i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions") names amx-int8/amx-bf16/amx-complex-amx-fp16 in CPUID 0x1E.1.EAX with "-mirror" suffix. To align with the naming style of corresponding macros, rename these feature words with "-alias" suffix. Since the commit 956b8f0fc38a is merged in v11.0 development cycle, it's safe to modify the names of feature words (before v11.0 is released). Signed-off-by: Zhao Liu --- target/i386/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 953770db9c9a..21dcfa47c351 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1314,7 +1314,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { [FEAT_1E_1_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { - "amx-int8-mirror", "amx-bf16-mirror", "amx-complex-mirror", "a= mx-fp16-mirror", + "amx-int8-alias", "amx-bf16-alias", "amx-complex-alias", "amx-= fp16-alias", "amx-fp8", NULL, "amx-tf32", "amx-avx512", "amx-movrs", NULL, NULL, NULL, NULL, NULL, NULL, NULL, --=20 2.34.1 From nobody Sat Apr 11 20:10:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; 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d="scan'208";a="217647976" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 3/5] i386/cpu: Remove unnecessary cache_info fields from builtin CPU model Date: Tue, 10 Mar 2026 22:08:17 +0800 Message-Id: <20260310140819.1563084-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150217613154100 Content-Type: text/plain; charset="utf-8" In x86_cpu_get_versioned_cache_info(), higher version CPU models will inherit cache_info from lower versions if the cache_info field is not specified, so there is no need to repeatedly set the same cache_info. Therefore, remove the repeated cache models from SapphireRapids-v6 (SapphireRapids-v4 has set the cache model), GraniteRapids-v5 (GraniteRapids-v3 has set) and SierraForest-v5 (SierraForest-v3 has set). Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 21dcfa47c351..c6323fee94bb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5264,7 +5264,6 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { { .version =3D 6, .note =3D "with cet-ss, cet-ibt, its-no", - .cache_info =3D &xeon_spr_cache_info, .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, @@ -5446,7 +5445,6 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { { .version =3D 5, .note =3D "with cet-ss, cet-ibt, its-no", - .cache_info =3D &xeon_gnr_cache_info, .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, @@ -5812,7 +5810,6 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { { .version =3D 5, .note =3D "with ITS_NO", - .cache_info =3D &xeon_srf_cache_info, .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, --=20 2.34.1 From nobody Sat Apr 11 20:10:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 10 Mar 2026 09:42:29 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 06:42:24 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 10 Mar 2026 06:42:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773150148; x=1804686148; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=23oFSQFeckjBSHClRj8x1vVwScp8+dwkHgm070uUpNo=; b=G7J1ffeP8LMAGbNChuzM4S1lpLYnD2RkPBhjlMDC32HtdGHRTLDwYZFJ c8ahDWmS9KsOBk4MIKkuTQfPgPAVB7feilZQuUsR7Y1K3bpENA+LtK4QD zP6XHMwb5cYRu1oF6G2EPT7buKrV2krHCXSzXjO9AogQiBGdAXa5opteK lysHgtsBf9kgvFgKLUHhkMzldw/aZt7Cky082l2R7TLnXvTMSh1q3BDUS Og01Ze1uBaRvoazfQNSeA3QXAEm9JEKIs4TgMEWrVnizK5uIaGiE/XFV4 ePb2D8cmAJMSCcP7a6WYX4z4LlYu9Y6vAn7KDHxVqgvaxwjiqasnbWDyG w==; X-CSE-ConnectionGUID: wTmKERFRR8CxeaG+M7cJDA== X-CSE-MsgGUID: jgJQQhnzQASvwdpZMkyaQg== X-IronPort-AV: E=McAfee;i="6800,10657,11725"; a="78048241" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="78048241" X-CSE-ConnectionGUID: o/W/iWanRrylRWIyUJhLwg== X-CSE-MsgGUID: Ee42vWskQ2Os8tM6v7sQxA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="217647985" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu Subject: [PATCH 4/5] i386/cpu: Adjust the note for CPU models with its-no Date: Tue, 10 Mar 2026 22:08:18 +0800 Message-Id: <20260310140819.1563084-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150198645154100 Content-Type: text/plain; charset="utf-8" For new versioned CPU models with its-no enabled, since CET was already enabled in previous versions, remove the related description from the notes of its-no related CPU models. Signed-off-by: Zhao Liu --- target/i386/cpu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c6323fee94bb..a3c8f523e85b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5263,7 +5263,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { }, { .version =3D 6, - .note =3D "with cet-ss, cet-ibt, its-no", + .note =3D "with its-no", .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, @@ -5444,7 +5444,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { }, { .version =3D 5, - .note =3D "with cet-ss, cet-ibt, its-no", + .note =3D "with its-no", .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, @@ -5809,7 +5809,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { }, { .version =3D 5, - .note =3D "with ITS_NO", + .note =3D "with its-no", .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, @@ -5963,7 +5963,7 @@ static const X86CPUDefinition builtin_x86_defs[] =3D { }, { .version =3D 3, - .note =3D "with cet-ss, cet-ibt, ITS_NO", + .note =3D "with its-no", .props =3D (PropValue[]) { { "its-no", "on" }, { /* end of list */ }, --=20 2.34.1 From nobody Sat Apr 11 20:10:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 10 Mar 2026 09:42:30 -0400 Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 06:42:25 -0700 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa007.fm.intel.com with ESMTP; 10 Mar 2026 06:42:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1773150149; x=1804686149; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=bN9Ea9R3MgXHRqo0PkJv/bfX8SYsbbsseRAhQ1lTJ9s=; b=U8oOvrB67hzSB/ZbxfyTgkx/tU3JNwfdCv7JPoKrIfo5TvkOVlbrI13D LpYY4CPkFTSCYI2qKBlw5HIXPjS/ob4Jcq55nKMQWyf5lDVDwjz4PEeI0 SXkyBbOLf/sY8LsT+5/YxbtUhaFww8fKE8GGTTFDvL1qvElucye5JRESx VwDgQxBRpywMcskQzuAIAmMVVflZ13aSlvHsUf/BxEuX8tLEofpvAty0s ngsAAR02OY2FRulLXnEwSj+FBUXlMPtkMOkZcT9uim3vCsykMDJ+mGWBP vFBvKnPeeOXUadm9BjLcV1vRUndvBagHy8K6ugX0jy1k2fBWzB5rNXTaf g==; X-CSE-ConnectionGUID: jbqIX5gDQl2kuUJW0aysvQ== X-CSE-MsgGUID: H9PI+lW9SDGO5n4dU1mDzg== X-IronPort-AV: E=McAfee;i="6800,10657,11725"; a="78048244" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="78048244" X-CSE-ConnectionGUID: kGA9/KI7SUG57tAPSes/Eg== X-CSE-MsgGUID: ofk3Bqi2TlmvsIdN9JzMKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="217647998" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, Zhao Liu , Zhijun Zeng , Chao Peng Subject: [PATCH 5/5] i386/cpu: Enable CPUID 0x1f & cache model for ClearwaterForest Date: Tue, 10 Mar 2026 22:08:19 +0800 Message-Id: <20260310140819.1563084-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260310140819.1563084-1-zhao1.liu@intel.com> References: <20260310140819.1563084-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.14; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1773150175481158500 Content-Type: text/plain; charset="utf-8" ClearwaterForest has CPUID 0x1f by default, so force enabling this leaf for it (ClearwaterForect-v3). And add the cache model to ClearwaterForest (v3) to better emulate its environment. The cache model is based on ClearwaterForest-AP (Advanced Performance): --- cache 0 --- cache type =3D data cache (1) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x40 (64) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 64 (size synth) =3D 32768 (32 KB) --- cache 1 --- cache type =3D instruction cache (2) cache level =3D 0x1 (1) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x0 (0) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x8 (8) number of sets =3D 0x80 (128) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 128 (size synth) =3D 65536 (64 KB) --- cache 2 --- cache type =3D unified cache (3) cache level =3D 0x2 (2) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x7 (7) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x1000 (4096) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D false number of sets (s) =3D 4096 (size synth) =3D 4194304 (4 MB) --- cache 3 --- cache type =3D unified cache (3) cache level =3D 0x3 (3) self-initializing cache level =3D true fully associative cache =3D false maximum IDs for CPUs sharing cache =3D 0x3ff (1023) maximum IDs for cores in pkg =3D 0x3f (63) system coherency line size =3D 0x40 (64) physical line partitions =3D 0x1 (1) ways of associativity =3D 0x10 (16) number of sets =3D 0x84000 (540672) WBINVD/INVD acts on lower caches =3D false inclusive to lower caches =3D false complex cache indexing =3D true number of sets (s) =3D 540672 (size synth) =3D 553648128 (528 MB) --- cache 4 --- cache type =3D no more caches (0) Suggested-by: Zhijun Zeng Suggested-by: Chao Peng Signed-off-by: Zhao Liu --- target/i386/cpu.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 94 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a3c8f523e85b..4b6aed770a15 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3318,6 +3318,97 @@ static const CPUCaches xeon_srf_cache_info =3D { }, }; =20 +static const CPUCaches xeon_cwf_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x0.EAX */ + .type =3D DATA_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x0.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x0.ECX */ + .sets =3D 64, + + /* CPUID 0x4.0x0.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 32 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l1i_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x1.EAX */ + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .self_init =3D true, + + /* CPUID 0x4.0x1.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 8, + + /* CPUID 0x4.0x1.ECX */ + .sets =3D 128, + + /* CPUID 0x4.0x1.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 64 * KiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_CORE, + }, + .l2_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x2.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 2, + .self_init =3D true, + + /* CPUID 0x4.0x2.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x2.ECX */ + .sets =3D 4096, + + /* CPUID 0x4.0x2.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D false, + + .size =3D 4 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_MODULE, + }, + .l3_cache =3D &(CPUCacheInfo) { + /* CPUID 0x4.0x3.EAX */ + .type =3D UNIFIED_CACHE, + .level =3D 3, + .self_init =3D true, + + /* CPUID 0x4.0x3.EBX */ + .line_size =3D 64, + .partitions =3D 1, + .associativity =3D 16, + + /* CPUID 0x4.0x3.ECX */ + .sets =3D 540672, + + /* CPUID 0x4.0x3.EDX */ + .no_invd_sharing =3D false, + .inclusive =3D false, + .complex_indexing =3D true, + + .size =3D 528 * MiB, + .share_level =3D CPU_TOPOLOGY_LEVEL_SOCKET, + }, +}; + static const CPUCaches yongfeng_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { /* CPUID 0x4.0x0.EAX */ @@ -5963,9 +6054,11 @@ static const X86CPUDefinition builtin_x86_defs[] =3D= { }, { .version =3D 3, - .note =3D "with its-no", + .note =3D "with its-no, cwf-ap cache model and 0x1f leaf", + .cache_info =3D &xeon_cwf_cache_info, .props =3D (PropValue[]) { { "its-no", "on" }, + { "x-force-cpuid-0x1f", "on" }, { /* end of list */ }, } }, --=20 2.34.1