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Mon, 09 Mar 2026 14:48:57 -0700 (PDT) From: Lucas Amaral To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, agraf@csgraf.de, Lucas Amaral Subject: [PATCH] target/arm/hvf: emulate ISV=0 data abort instructions Date: Mon, 9 Mar 2026 18:48:52 -0300 Message-ID: <20260309214852.92545-1-lucaaamaral@gmail.com> X-Mailer: git-send-email 2.52.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1236; envelope-from=lucaaamaral@gmail.com; helo=mail-dl1-x1236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_BARE_IP_2=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 09 Mar 2026 18:16:41 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1773094661480154100 Content-Type: text/plain; charset="utf-8" On Apple Silicon, HVF exits with ISV=3D0 (no syndrome information) for STP/LDP/STNP/LDNP, SIMD/FP load/stores, and DC cache maintenance instructions that access MMIO regions. The existing code asserted ISV!=3D0, crashing the VM. Decode the faulting instruction from guest memory and emulate: - Load/Store Pair (STP/LDP/STNP/LDNP) for GPR and SIMD registers - Single Load/Store with writeback and SIMD/FP variants - DC system instructions (NOP on MMIO regions) - LDPSW (sign-extending load pair) For pair instructions, compute the effective virtual address from the base register to handle page-straddling accesses correctly. HPFAR_EL2 reports the faulting page, not the effective address, so using the IPA directly would produce wrong results when an STP straddles an HVF-mapped / MMIO boundary. Tested with virtio-gpu Venus blob resources on macOS ARM64. Signed-off-by: Lucas Amaral --- target/arm/hvf/hvf.c | 309 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 306 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index d79469c..87ddcdb 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1871,10 +1871,313 @@ static int hvf_handle_exception(CPUState *cpu, hv_= vcpu_exit_exception_t *excp) assert(!s1ptw); =20 /* - * TODO: ISV will be 0 for SIMD or SVE accesses. - * Inject the exception into the guest. + * ISV=3D0: syndrome doesn't carry access size/register info. + * This happens for STP/LDP/STNP/LDNP, SIMD/SVE load/stores, + * and DC (data cache) maintenance instructions. + * + * Sync all CPU state (including TTBR/TCR/SCTLR for page table + * walk) and decode the faulting instruction from guest memory. */ - assert(isv); + if (!isv) { + ARMCPU *arm_cpu =3D ARM_CPU(cpu); + CPUARMState *env =3D &arm_cpu->env; + uint32_t insn; + + /* + * Sync system registers (TTBR, TCR, SCTLR, etc.) from HVF + * so cpu_memory_rw_debug can walk guest page tables. + */ + cpu_synchronize_state(cpu); + + if (cpu_memory_rw_debug(cpu, env->pc, + (uint8_t *)&insn, 4, false) !=3D 0) { + error_report("HVF: ISV=3D0 at ipa=3D0x%" PRIx64 + " -- cannot read insn at pc=3D0x%" PRIx64, + ipa, (uint64_t)env->pc); + goto isv0_inject_fault; + } + insn =3D le32_to_cpu(insn); + + /* + * System instructions (DC CIVAC, DC CVAC, etc.): + * bits [31:22] =3D 1101010100 identifies MRS/MSR/SYS class. + * Cache maintenance on MMIO regions is a harmless NOP. + */ + if ((insn & 0xFFC00000) =3D=3D 0xD5000000) { + advance_pc =3D true; + break; + } + + /* + * Load/Store Pair (STP/LDP/STNP/LDNP): + * bits [29:27] =3D 101 identifies this instruction class. + * Supports both integer (GPR) and SIMD/FP register pairs. + */ + if ((insn & 0x38000000) =3D=3D 0x28000000) { + uint32_t opc =3D extract32(insn, 30, 2); + bool is_vec =3D extract32(insn, 26, 1); + bool is_load =3D extract32(insn, 22, 1); + uint32_t rt =3D extract32(insn, 0, 5); + uint32_t rt2 =3D extract32(insn, 10, 5); + uint32_t rn =3D extract32(insn, 5, 5); + uint32_t type =3D extract32(insn, 23, 3); + bool writeback =3D (type =3D=3D 1 || type =3D=3D 3); + uint32_t esize; + int32_t imm7 =3D sextract32(insn, 15, 7); + + if (!is_vec) { + esize =3D (opc & 2) ? 8 : 4; + } else { + esize =3D 4u << opc; /* 4, 8, or 16 bytes */ + } + + int64_t stp_offset =3D (int64_t)imm7 * esize; + + /* + * Compute the effective virtual address from the base + * register and immediate offset. HPFAR_EL2 reports + * the faulting page, not the effective address, so we + * must derive the VA from the instruction encoding. + * + * After cpu_synchronize_state(), env->xregs[0..30] are + * GPRs and env->xregs[31] is the current SP (restored + * via aarch64_restore_sp). + * + * Using the VA with cpu_memory_rw_debug() correctly + * splits page-straddling accesses via guest page tables. + */ + uint64_t rn_va =3D env->xregs[rn]; + /* post-index: access at unmodified base */ + uint64_t va =3D (type =3D=3D 1) ? rn_va : rn_va + stp_offs= et; + + if (is_load =3D=3D iswrite) { + error_report("HVF: ISV=3D0 load/write mismatch at " + "ipa=3D0x%" PRIx64, ipa); + goto isv0_inject_fault; + } + + if (iswrite) { + /* Store pair */ + if (!is_vec) { + uint64_t val1 =3D env->xregs[rt]; + uint64_t val2 =3D env->xregs[rt2]; + uint8_t buf[16]; /* max 2 x 8 bytes */ + memcpy(buf, &val1, esize); + memcpy(buf + esize, &val2, esize); + cpu_memory_rw_debug(cpu, va, buf, + 2 * esize, true); + } else { + /* + * SIMD STP: register data is in env->vfp.zregs[] + * after cpu_synchronize_state(). + * esize=3D4: S reg, esize=3D8: D reg, esize=3D16:= Q reg + */ + uint8_t buf[32]; /* max 2 x 16 bytes */ + memcpy(buf, &env->vfp.zregs[rt], esize); + memcpy(buf + esize, + &env->vfp.zregs[rt2], esize); + cpu_memory_rw_debug(cpu, va, buf, + 2 * esize, true); + } + } else { + /* Load pair */ + if (!is_vec) { + uint64_t val1 =3D 0, val2 =3D 0; + uint8_t buf[16]; + memset(buf, 0, sizeof(buf)); + cpu_memory_rw_debug(cpu, va, buf, + 2 * esize, false); + memcpy(&val1, buf, esize); + memcpy(&val2, buf + esize, esize); + if (opc =3D=3D 1 && !is_vec) { + /* LDPSW: sign-extend 32-bit to 64-bit */ + val1 =3D (int64_t)(int32_t)val1; + val2 =3D (int64_t)(int32_t)val2; + } + hvf_set_reg(cpu, rt, val1); + hvf_set_reg(cpu, rt2, val2); + } else { + /* SIMD LDP */ + uint8_t buf[32]; + memset(buf, 0, sizeof(buf)); + cpu_memory_rw_debug(cpu, va, buf, + 2 * esize, false); + memset(&env->vfp.zregs[rt], 0, + sizeof(env->vfp.zregs[rt])); + memset(&env->vfp.zregs[rt2], 0, + sizeof(env->vfp.zregs[rt2])); + memcpy(&env->vfp.zregs[rt], buf, esize); + memcpy(&env->vfp.zregs[rt2], + buf + esize, esize); + cpu->vcpu_dirty =3D true; + } + } + + /* Handle base register writeback (pre/post-index) */ + if (writeback) { + env->xregs[rn] =3D env->xregs[rn] + stp_offset; + cpu->vcpu_dirty =3D true; + } + + advance_pc =3D true; + break; + } + + /* + * Load/Store Register (single): + * bits [29:27] =3D 111, bit [25] =3D 0. + * Covers immediate (unscaled, post-index, pre-index), + * unsigned offset, and register offset variants. + * + * ISV=3D0 for: writeback variants (pre/post-indexed) and + * all SIMD/FP loads/stores. + */ + if ((insn & 0x3A000000) =3D=3D 0x38000000) { + uint32_t size_field =3D extract32(insn, 30, 2); + bool is_vec =3D extract32(insn, 26, 1); + uint32_t opc =3D extract32(insn, 22, 2); + bool is_unsigned =3D extract32(insn, 24, 1); + bool bit21 =3D extract32(insn, 21, 1); + uint32_t rn =3D extract32(insn, 5, 5); + uint32_t rt =3D extract32(insn, 0, 5); + uint32_t sub_type =3D extract32(insn, 10, 2); + bool is_reg =3D !is_unsigned && bit21; + + /* + * [24]=3D0, [21]=3D1, [11:10]!=3D10 could be atomic ops + * (LDADD, SWP, CAS, etc.) -- not handled. + */ + if (is_reg && sub_type !=3D 2) { + goto isv0_inject_fault; + } + + bool writeback =3D !is_unsigned && !is_reg + && (sub_type =3D=3D 1 || sub_type =3D=3D = 3); + + uint32_t esize; + bool is_load; + bool is_signed =3D false; + uint32_t sign_extend_to =3D 0; + + if (!is_vec) { + esize =3D 1u << size_field; + switch (opc) { + case 0: /* STR */ + is_load =3D false; + break; + case 1: /* LDR */ + is_load =3D true; + break; + case 2: + is_load =3D true; /* LDRS->64= */ + is_signed =3D true; + sign_extend_to =3D 8; + break; + case 3: + if (size_field =3D=3D 3) { + /* PRFM -- prefetch is NOP on MMIO */ + advance_pc =3D true; + goto isv0_done; + } + is_load =3D true; /* LDRS->32= */ + is_signed =3D true; + sign_extend_to =3D 4; + break; + } + } else { + /* SIMD/FP: size+opc determines element width */ + is_load =3D (opc & 1); + if (opc >=3D 2 && size_field =3D=3D 0) { + esize =3D 16; /* Q register (128-bit) */ + } else if (opc < 2) { + esize =3D 1u << size_field; + } else { + goto isv0_inject_fault; + } + } + + if (is_load =3D=3D iswrite) { + error_report("HVF: ISV=3D0 LDR/STR load/write mismatch= " + "at ipa=3D0x%" PRIx64, ipa); + goto isv0_inject_fault; + } + + /* Perform memory access */ + if (!is_load) { + if (!is_vec) { + uint64_t val =3D hvf_get_reg(cpu, rt); + address_space_write(as, ipa, + MEMTXATTRS_UNSPECIFIED, + &val, esize); + } else { + address_space_write(as, ipa, + MEMTXATTRS_UNSPECIFIED, + &env->vfp.zregs[rt], esize); + } + } else { + if (!is_vec) { + uint64_t val =3D 0; + address_space_read(as, ipa, + MEMTXATTRS_UNSPECIFIED, + &val, esize); + if (is_signed) { + switch (esize) { + case 1: + val =3D (int64_t)(int8_t)val; + break; + case 2: + val =3D (int64_t)(int16_t)val; + break; + case 4: + val =3D (int64_t)(int32_t)val; + break; + } + if (sign_extend_to =3D=3D 4) { + val &=3D 0xFFFFFFFF; + } + } + hvf_set_reg(cpu, rt, val); + } else { + /* SIMD/FP load */ + memset(&env->vfp.zregs[rt], 0, + sizeof(env->vfp.zregs[rt])); + address_space_read(as, ipa, + MEMTXATTRS_UNSPECIFIED, + &env->vfp.zregs[rt], esize); + cpu->vcpu_dirty =3D true; + } + } + + /* Base register writeback (post/pre-indexed) */ + if (writeback) { + int32_t imm9 =3D sextract32(insn, 12, 9); + env->xregs[rn] =3D env->xregs[rn] + imm9; + cpu->vcpu_dirty =3D true; + } + + advance_pc =3D true; + goto isv0_done; + } + +isv0_inject_fault: + /* + * Inject data abort into guest for unrecognized or + * inconsistent ISV=3D0 instructions. The guest kernel + * will deliver SIGBUS to the faulting process. + */ + { + int target_el =3D 1; + bool same_el =3D arm_current_el(env) =3D=3D target_el; + uint32_t esr =3D syn_data_abort_no_iss(same_el, + /*fnv=3D*/1, /*ea=3D*/0, /*cm=3D*/0, + /*s1ptw=3D*/0, iswrite, /*fsc=3D*/0x10); + env->exception.vaddress =3D ipa; + hvf_raise_exception(cpu, EXCP_DATA_ABORT, + esr, target_el); + } +isv0_done: + break; + } =20 /* * Emulate MMIO. --=20 2.52.0