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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 8/8] hw/arm/smmuv3-accel: Introduce _AUTO support for OAS Date: Mon, 9 Mar 2026 12:21:19 -0700 Message-ID: <20260309192119.870186-9-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY1P220CA0018.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:5c3::8) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: cd8b12fd-c466-4df6-7b42-08de7e113756 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084326617158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 OAS property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving OAS from IDR5. Set the default oas value to auto. The default Output Address Size used to be 44-bit, but we change it to match what the host IOMMU properties report so that users do not have to introspect host IDR5 for the OAS. This keeps the OAS value advertised by the virtual SMMU compatible with the capabilities of the host SMMUv3, so that the intermediate physical addresses (IPA) consumed by host SMMU for stage-2 translation do not exceed the host's max supported IPA size. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 11 +++++++++-- hw/arm/smmuv3.c | 11 ++++++----- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bd27b0da7c..03950a4cef 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -71,6 +71,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, FIELD_EX32(info->idr[1], IDR1, SSIDSIZE)); } =20 + /* Update OAS if auto from info */ + if (s->oas =3D=3D OAS_MODE_AUTO) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, + FIELD_EX32(info->idr[5], IDR5, OAS)); + } + accel->auto_finalised =3D true; } =20 @@ -898,7 +904,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s) } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas =3D=3D SMMU_OAS_48BIT) { + if (s->oas =3D=3D OAS_MODE_48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } =20 @@ -979,7 +985,8 @@ void smmuv3_accel_init(SMMUv3State *s) =20 if (s->ats =3D=3D ON_OFF_AUTO_AUTO || s->ril =3D=3D ON_OFF_AUTO_AUTO || - s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO || + s->oas =3D=3D OAS_MODE_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bc03353759..4fc4ed2c06 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1982,7 +1982,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } - if (s->oas !=3D SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } @@ -2000,8 +2000,9 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); + if (s->oas !=3D OAS_MODE_AUTO && s->oas !=3D OAS_MODE_44 && + s->oas !=3D OAS_MODE_48) { + error_setg(errp, "OAS can only be set to auto, 44 bits, or 48 bits= "); return false; } =20 @@ -2131,7 +2132,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_AUTO), }; @@ -2168,7 +2169,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "platform has ATS support before enabling this"); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ae8158a5c3..3bfee63396 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,7 +72,7 @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; =20 --=20 2.43.0