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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 4/8] hw/arm/smmuv3-accel: Introduce _AUTO support for RIL Date: Mon, 9 Mar 2026 12:21:15 -0700 Message-ID: <20260309192119.870186-5-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR05CA0085.namprd05.prod.outlook.com (2603:10b6:a03:e0::26) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: 60632f74-5ad9-40be-dd7b-08de7e113255 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084216052158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Range Invalidation support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3. Set the default value of RIL to auto. The default for RIL support used to be set to on, but we change it to match what the host IOMMU properties report so that users do not have to introspect host IDR3 for Range Invalidation support. The RIL support needs to be compatible with host SMMUv3 if accelerated mode is enabled. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 20 +++++++++++++++++--- hw/arm/smmuv3.c | 4 ++-- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 8fec335557..02e3f7a9f3 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -58,6 +58,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, FIELD_EX32(info->idr[0], IDR0, ATS)); } =20 + /* Update RIL if auto from info */ + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, + FIELD_EX32(info->idr[3], IDR3, RIL)); + } + accel->auto_finalised =3D true; } =20 @@ -854,8 +860,15 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* + * Only override RIL if user explicitly set ON or OFF. + * AUTO will be resolved later when host info is available. + */ + if (s->ril =3D=3D ON_OFF_AUTO_ON) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); + } else if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* Only override ATS if user explicitly set ON or OFF */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { @@ -941,7 +954,8 @@ void smmuv3_accel_init(SMMUv3State *s) bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); =20 - if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + if (s->ats =3D=3D ON_OFF_AUTO_AUTO || + s->ril =3D=3D ON_OFF_AUTO_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 197ba7c77b..7791e5294d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1973,7 +1973,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) #endif =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2133,7 +2133,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 2ca49ded36..9124bfe751 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0