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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen , Shameer Kolothum Subject: [RFC PATCH 1/8] hw/arm/smmuv3-accel: Add helper for resolving auto parameters Date: Mon, 9 Mar 2026 12:21:12 -0700 Message-ID: <20260309192119.870186-2-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR11CA0075.namprd11.prod.outlook.com (2603:10b6:a03:f4::16) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: 7aa098d4-1c9f-438b-edd3-08de7e112bd2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084186286154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce smmuv3_accel_auto_finalise() to resolve properties that are set to 'auto' for accelerated SMMUv3. This helper function allows properties such as ATS, RIL, SSIDSIZE, and OAS support to be resolved from host IOMMU values, while avoiding triggering auto-resolved values for hot-plugged devices. Auto mode requires at least one cold-plugged device to retrieve and finalise these properties, and we fail boot if that is not the case. Subsequent patches will make use of this helper to set the values when we convert the values to OnOffAuto. New auto_mode and auto_finalised bool members are added to SMMUv3AccelState. smmuv3_accel_init() will set auto_mode to true when 'auto' is detected for the accel SMMUv3 properties. smmuv3_accel_auto_finalise() will set auto_finalised to true after all 'auto' properties are resolved, and subsequent calls to this function will return early if auto_finalised is set to true. Suggested-by: Shameer Kolothum Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 38 +++++++++++++++++++++++++++++++++----- hw/arm/smmuv3-accel.h | 2 ++ 2 files changed, 35 insertions(+), 5 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 17306cd04b..617629bacd 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -35,11 +35,34 @@ static int smmuv3_oas_bits(uint32_t oas) return map[oas]; } =20 +static void smmuv3_accel_auto_finalise(SMMUv3State *s, PCIDevice *pdev, + struct iommu_hw_info_arm_smmuv3 *in= fo) { + SMMUv3AccelState *accel =3D s->s_accel; + + /* Return if no auto for any or finalised already */ + if (!accel->auto_mode || accel->auto_finalised) { + return; + } + + /* We can't update if device is hotplugged */ + if (DEVICE(pdev)->hotplugged) { + warn_report("arm-smmuv3: 'auto' feature property detected, but hos= t " + "value cannot be applied for hot-plugged device; using= " + "existing value"); + return; + } + + accel->auto_finalised =3D true; +} + static bool smmuv3_accel_check_hw_compatible(SMMUv3State *s, struct iommu_hw_info_arm_smmuv3 *info, + PCIDevice *pdev, Error **errp) { + smmuv3_accel_auto_finalise(s, pdev, info); + /* QEMU SMMUv3 supports both linear and 2-level stream tables */ if (FIELD_EX32(info->idr[0], IDR0, STLEVEL) !=3D FIELD_EX32(s->idr[0], IDR0, STLEVEL)) { @@ -124,7 +147,7 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, =20 static bool smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev, - Error **errp) + PCIDevice *pdev, Error **errp) { struct iommu_hw_info_arm_smmuv3 info; uint32_t data_type; @@ -142,7 +165,7 @@ smmuv3_accel_hw_compatible(SMMUv3State *s, HostIOMMUDev= iceIOMMUFD *idev, return false; } =20 - if (!smmuv3_accel_check_hw_compatible(s, &info, errp)) { + if (!smmuv3_accel_check_hw_compatible(s, &info, pdev, errp)) { return false; } return true; @@ -595,6 +618,7 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus, = void *opaque, int devfn, SMMUv3State *s =3D ARM_SMMUV3(bs); SMMUPciBus *sbus =3D smmu_get_sbus(bs, bus); SMMUv3AccelDevice *accel_dev =3D smmuv3_accel_get_dev(bs, sbus, bus, d= evfn); + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), devfn); =20 if (!idev) { return true; @@ -613,7 +637,7 @@ static bool smmuv3_accel_set_iommu_device(PCIBus *bus, = void *opaque, int devfn, * Check the host SMMUv3 associated with the dev is compatible with the * QEMU SMMUv3 accel. */ - if (!smmuv3_accel_hw_compatible(s, idev, errp)) { + if (!smmuv3_accel_hw_compatible(s, idev, pdev, errp)) { return false; } =20 @@ -867,8 +891,12 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Err= or **errp) =20 void smmuv3_accel_reset(SMMUv3State *s) { - /* Attach a HWPT based on GBPA reset value */ - smmuv3_accel_attach_gbpa_hwpt(s, NULL); + if (s->s_accel && s->s_accel->auto_mode && !s->s_accel->auto_finalised= ) { + error_report("AUTO mode specified but properties not finalised."); + exit(1); + } + /* Attach a HWPT based on GBPA reset value */ + smmuv3_accel_attach_gbpa_hwpt(s, NULL); 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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 2/8] hw/arm/smmuv3-accel: Introduce _AUTO support for ATS Date: Mon, 9 Mar 2026 12:21:13 -0700 Message-ID: <20260309192119.870186-3-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BY1P220CA0017.NAMP220.PROD.OUTLOOK.COM (2603:10b6:a03:5c3::6) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: 6df68b1e-4670-4ec6-4bd8-08de7e112ebe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084212186158501 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Address Translation Services support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving ATS capability from IDR0. Set the default value of ATS to auto. The default for ATS support used to be set to off, but we change it to match what the host IOMMU properties report. Add a "ats-enabled" read-only property for smmuv3 to address an expected bool for the "ats" property in iort_smmuv3_devices(). Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 25 +++++++++++++++++++++++-- hw/arm/smmuv3.c | 12 ++++++++++-- hw/arm/virt-acpi-build.c | 2 +- include/hw/arm/smmuv3.h | 2 +- 4 files changed, 35 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 617629bacd..8fec335557 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -52,6 +52,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, return; } =20 + /* Update ATS if auto from info */ + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, + FIELD_EX32(info->idr[0], IDR0, ATS)); + } + accel->auto_finalised =3D true; } =20 @@ -124,6 +130,13 @@ smmuv3_accel_check_hw_compatible(SMMUv3State *s, smmuv3_oas_bits(FIELD_EX32(s->idr[5], IDR5, OAS))); return false; } + /* Check ATS value opted is compatible with Host SMMUv3 */ + if (FIELD_EX32(info->idr[0], IDR0, ATS) < + FIELD_EX32(s->idr[0], IDR0, ATS)) { + error_setg(errp, "Host SMMUv3 doesn't support Address Translation" + " Services"); + return false; + } =20 /* QEMU SMMUv3 supports GRAN4K/GRAN16K/GRAN64K translation granules */ if (FIELD_EX32(info->idr[5], IDR5, GRAN4K) !=3D @@ -844,8 +857,12 @@ void smmuv3_accel_idr_override(SMMUv3State *s) /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); =20 - /* QEMU SMMUv3 has no ATS. Advertise ATS if opt-in by property */ - s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, s->ats); + /* Only override ATS if user explicitly set ON or OFF */ + if (s->ats =3D=3D ON_OFF_AUTO_ON) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 1); + } else if (s->ats =3D=3D ON_OFF_AUTO_OFF) { + s->idr[0] =3D FIELD_DP32(s->idr[0], IDR0, ATS, 0); + } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ if (s->oas =3D=3D SMMU_OAS_48BIT) { @@ -923,4 +940,8 @@ void smmuv3_accel_init(SMMUv3State *s) s->s_accel =3D g_new0(SMMUv3AccelState, 1); bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); + + if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + s->s_accel->auto_mode =3D true; + } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 068108e49b..197ba7c77b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -317,6 +317,12 @@ static void smmuv3_init_id_regs(SMMUv3State *s) smmuv3_accel_idr_override(s); } =20 +static bool get_ats_enabled(Object *obj, Error **errp) +{ + SMMUv3State *s =3D ARM_SMMUV3(obj); + return FIELD_EX32(s->idr[0], IDR0, ATS); +} + static void smmuv3_reset(SMMUv3State *s) { s->cmdq.base =3D deposit64(s->cmdq.base, 0, 5, SMMU_CMDQS); @@ -1971,7 +1977,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } - if (s->ats) { + if (s->ats =3D=3D ON_OFF_AUTO_ON) { error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } @@ -2128,7 +2134,7 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), - DEFINE_PROP_BOOL("ats", SMMUv3State, ats, false), + DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), }; @@ -2153,6 +2159,8 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) dc->hotpluggable =3D false; dc->user_creatable =3D true; =20 + object_class_property_add_bool(klass, "ats-enabled", get_ats_enabled, = NULL); + object_class_property_set_description(klass, "accel", "Enable SMMUv3 accelerator support. Allows host SMMUv3 to be " "configured in nested mode for vfio-pci dev assignment"); diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 719d2f994e..6c77fc5f6a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -402,7 +402,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaqu= e) =20 bus =3D PCI_BUS(object_property_get_link(obj, "primary-bus", &error_ab= ort)); sdev.accel =3D object_property_get_bool(obj, "accel", &error_abort); - sdev.ats =3D object_property_get_bool(obj, "ats", &error_abort); + sdev.ats =3D object_property_get_bool(obj, "ats-enabled", &error_abort= ); pbus =3D PLATFORM_BUS_DEVICE(vms->platform_bus_dev); sbdev =3D SYS_BUS_DEVICE(obj); sdev.base =3D platform_bus_get_mmio_addr(pbus, sbdev, 0); diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 26b2fc42fd..2ca49ded36 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -70,7 +70,7 @@ struct SMMUv3State { uint64_t msi_gpa; Error *migration_blocker; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084244689154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Add an "ats" OnOffAuto property to vfio-pci. When the device has an ATS extended capability in config space but we should not expose it (ats=3Doff, or ats=3Dauto and kernel reports IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED), mask the capability so the guest does not see it. This aligns with the kernel's per-device effective ATS reporting and allows omitting ATS capability when the vIOMMU has ats=3Doff. Suggested-by: Shameer Kolothum Signed-off-by: Nathan Chen --- backends/iommufd.c | 15 +++++++ hw/vfio/pci.c | 63 ++++++++++++++++++++++++++++++ hw/vfio/pci.h | 1 + include/system/host_iommu_device.h | 10 +++++ 4 files changed, 89 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index acfab907c0..d1e9d4dec3 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -22,6 +22,13 @@ #include "hw/vfio/vfio-device.h" #include #include +/* + * Until kernel UAPI is synced via scripts; + * matches include/uapi/linux/iommufd.h + */ +#ifndef IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED +#define IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED (1 << 3) +#endif =20 static const char *iommufd_fd_name(IOMMUFDBackend *be) { @@ -570,6 +577,13 @@ static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod,= int cap, Error **errp) } } =20 +static bool hiod_iommufd_support_ats(HostIOMMUDevice *hiod) +{ + HostIOMMUDeviceCaps *caps =3D &hiod->caps; + + return !(caps->hw_caps & IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED); +} + static bool hiod_iommufd_get_pasid_info(HostIOMMUDevice *hiod, PasidInfo *pasid_info) { @@ -592,6 +606,7 @@ static void hiod_iommufd_class_init(ObjectClass *oc, co= nst void *data) =20 hioc->get_cap =3D hiod_iommufd_get_cap; hioc->get_pasid_info =3D hiod_iommufd_get_pasid_info; + hioc->support_ats =3D hiod_iommufd_support_ats; }; =20 static const TypeInfo types[] =3D { diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index c89f3fbea3..62b7cc08e6 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -49,6 +49,10 @@ #include "system/iommufd.h" #include "vfio-migration-internal.h" #include "vfio-helpers.h" +#ifdef CONFIG_IOMMUFD +#include "system/host_iommu_device.h" +#include "linux/iommufd.h" +#endif =20 /* Protected by BQL */ static KVMRouteChange vfio_route_change; @@ -2550,10 +2554,53 @@ static bool vfio_pci_synthesize_pasid_cap(VFIOPCIDe= vice *vdev, Error **errp) return true; } =20 +/* + * Determine whether ATS capability should be advertised for @vdev, based = on + * whether it was enabled on the command line and whether it is supported + * according to the kernel's IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED bit. + * + * Store whether ATS capability should be advertised in @ats_need. + * + * Return false if kernel enables IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED + * and ATS is effectively unsupported. + */ +static bool vfio_pci_ats_requested_and_supported(VFIOPCIDevice *vdev, + bool *ats_need, Error **e= rrp) +{ + HostIOMMUDevice *hiod =3D vdev->vbasedev.hiod; + HostIOMMUDeviceClass *hiodc; + bool ats_supported; + + if (vdev->ats =3D=3D ON_OFF_AUTO_OFF) { + *ats_need =3D false; + return true; + } + + *ats_need =3D true; + if (!hiod) { + return true; + } + hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); + if (!hiodc || !hiodc->support_ats) { + return true; + } + + ats_supported =3D hiodc->support_ats(hiod); + if (vdev->ats =3D=3D ON_OFF_AUTO_ON && !ats_supported) { + error_setg(errp, "vfio: ATS requested but not supported by kernel"= ); + *ats_need =3D false; + return false; + } + + *ats_need =3D ats_supported; + return true; +} + static void vfio_add_ext_cap(VFIOPCIDevice *vdev) { PCIDevice *pdev =3D PCI_DEVICE(vdev); bool pasid_cap_added =3D false; + bool ats_needed =3D false; Error *err =3D NULL; uint32_t header; uint16_t cap_id, next, size; @@ -2603,6 +2650,11 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0); pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0); =20 + if (!vfio_pci_ats_requested_and_supported(vdev, &ats_needed, &err)) { + error_report_err(err); + err =3D NULL; + } + for (next =3D PCI_CONFIG_SPACE_SIZE; next; next =3D PCI_EXT_CAP_NEXT(pci_get_long(config + next))) { header =3D pci_get_long(config + next); @@ -2640,6 +2692,16 @@ static void vfio_add_ext_cap(VFIOPCIDevice *vdev) case PCI_EXT_CAP_ID_PASID: pasid_cap_added =3D true; /* fallthrough */ + case PCI_EXT_CAP_ID_ATS: + /* + * If ATS is requested and supported according to the kernel, = add + * the ATS capability. If not supported according to the kerne= l or + * disabled on the qemu command line, omit the ATS cap. + */ + if (ats_needed) { + pcie_add_capability(pdev, cap_id, cap_ver, next, size); + } + break; default: pcie_add_capability(pdev, cap_id, cap_ver, next, size); } @@ -3819,6 +3881,7 @@ static const Property vfio_pci_properties[] =3D { #ifdef CONFIG_IOMMUFD DEFINE_PROP_LINK("iommufd", VFIOPCIDevice, vbasedev.iommufd, TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), + DEFINE_PROP_ON_OFF_AUTO("ats", VFIOPCIDevice, ats, ON_OFF_AUTO_AUTO), #endif DEFINE_PROP_BOOL("skip-vsc-check", VFIOPCIDevice, skip_vsc_check, true= ), DEFINE_PROP_UINT16("x-vpasid-cap-offset", VFIOPCIDevice, diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index d6495d7f29..514a9197ce 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -191,6 +191,7 @@ struct VFIOPCIDevice { VFIODisplay *dpy; Notifier irqchip_change_notifier; VFIOPCICPR cpr; + OnOffAuto ats; }; =20 /* Use uin32_t for vendor & device so PCI_ANY_ID expands and cannot match = hw */ diff --git a/include/system/host_iommu_device.h b/include/system/host_iommu= _device.h index f000301583..44c56e87bb 100644 --- a/include/system/host_iommu_device.h +++ b/include/system/host_iommu_device.h @@ -133,6 +133,16 @@ struct HostIOMMUDeviceClass { * Returns: true on success, false on failure. */ bool (*get_pasid_info)(HostIOMMUDevice *hiod, PasidInfo *pasid_info); + /** + * @support_ats: Return whether ATS is supported for the device + * associated with @hiod host IOMMU device, checking if the + * IOMMU_HW_CAP_PCI_ATS_NOT_SUPPORTED capability bit is set. + * + * @hiod: handle to the host IOMMU device + * + * Returns: true on success, false on failure + */ + bool (*support_ats)(HostIOMMUDevice *hiod); }; =20 /* --=20 2.43.0 From nobody Sat Apr 11 21:30:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); dmarc=pass(p=reject dis=none) header.from=nvidia.com ARC-Seal: i=2; a=rsa-sha256; t=1773084215; cv=pass; d=zohomail.com; s=zohoarc; b=JUIQmiDQK3E8UnXWfsaUFMx5CWUMwIC9MrRlSuwRemR5wDQOwEroMitMneCeifQhRMUto4nQfxMJmw80HVyynMlwQKo3ixIaIw1EBe8bF/o35YSEmvsFfOw9pdewZ9C9sNEHxuGItST81KyBSr84h6K08z7HJD4wQIGnCJfp1+s= ARC-Message-Signature: i=2; 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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 4/8] hw/arm/smmuv3-accel: Introduce _AUTO support for RIL Date: Mon, 9 Mar 2026 12:21:15 -0700 Message-ID: <20260309192119.870186-5-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR05CA0085.namprd05.prod.outlook.com (2603:10b6:a03:e0::26) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: 60632f74-5ad9-40be-dd7b-08de7e113255 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084216052158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 Range Invalidation support property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving RIL capability from IDR3. Set the default value of RIL to auto. The default for RIL support used to be set to on, but we change it to match what the host IOMMU properties report so that users do not have to introspect host IDR3 for Range Invalidation support. The RIL support needs to be compatible with host SMMUv3 if accelerated mode is enabled. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 20 +++++++++++++++++--- hw/arm/smmuv3.c | 4 ++-- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 8fec335557..02e3f7a9f3 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -58,6 +58,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, FIELD_EX32(info->idr[0], IDR0, ATS)); } =20 + /* Update RIL if auto from info */ + if (s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, + FIELD_EX32(info->idr[3], IDR3, RIL)); + } + accel->auto_finalised =3D true; } =20 @@ -854,8 +860,15 @@ void smmuv3_accel_idr_override(SMMUv3State *s) return; } =20 - /* By default QEMU SMMUv3 has RIL. Update IDR3 if user has disabled it= */ - s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, s->ril); + /* + * Only override RIL if user explicitly set ON or OFF. + * AUTO will be resolved later when host info is available. + */ + if (s->ril =3D=3D ON_OFF_AUTO_ON) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 1); + } else if (s->ril =3D=3D ON_OFF_AUTO_OFF) { + s->idr[3] =3D FIELD_DP32(s->idr[3], IDR3, RIL, 0); + } =20 /* Only override ATS if user explicitly set ON or OFF */ if (s->ats =3D=3D ON_OFF_AUTO_ON) { @@ -941,7 +954,8 @@ void smmuv3_accel_init(SMMUv3State *s) bs->iommu_ops =3D &smmuv3_accel_ops; smmuv3_accel_as_init(s); =20 - if (s->ats =3D=3D ON_OFF_AUTO_AUTO) { + if (s->ats =3D=3D ON_OFF_AUTO_AUTO || + s->ril =3D=3D ON_OFF_AUTO_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 197ba7c77b..7791e5294d 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1973,7 +1973,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) #endif =20 if (!s->accel) { - if (!s->ril) { + if (s->ril =3D=3D ON_OFF_AUTO_OFF) { error_setg(errp, "ril can only be disabled if accel=3Don"); return false; } @@ -2133,7 +2133,7 @@ static const Property smmuv3_properties[] =3D { /* GPA of MSI doorbell, for SMMUv3 accel use. */ DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), /* RIL can be turned off for accel cases */ - DEFINE_PROP_BOOL("ril", SMMUv3State, ril, true), + DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 2ca49ded36..9124bfe751 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -69,7 +69,7 @@ struct SMMUv3State { struct SMMUv3AccelState *s_accel; uint64_t msi_gpa; Error *migration_blocker; - bool ril; + OnOffAuto ril; OnOffAuto ats; uint8_t oas; uint8_t ssidsize; --=20 2.43.0 From nobody Sat Apr 11 21:30:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 5/8] qdev: Add a SsidSizeMode property Date: Mon, 9 Mar 2026 12:21:16 -0700 Message-ID: <20260309192119.870186-6-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ2PR07CA0023.namprd07.prod.outlook.com (2603:10b6:a03:505::9) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: b3cff247-153d-4360-b8a1-08de7e113381 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084226179158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce a new enum type property allowing to set a Substream ID size for HW-accelerated smmuv3. Values are auto and 0..20. The auto value allows SSID size property to be derived from host IOMMU capabilities. A value of 0 disables SubstreamID, while non-zero values specify the SSID size in bits. Signed-off-by: Nathan Chen --- hw/core/qdev-properties-system.c | 14 ++++++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 15 +++++++++++++++ qapi/pragma.json | 1 + 4 files changed, 33 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index a402321f42..4aca1d4326 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -18,6 +18,7 @@ #include "qapi/qapi-types-block.h" #include "qapi/qapi-types-machine.h" #include "qapi/qapi-types-migration.h" +#include "qapi/qapi-types-misc-arm.h" #include "qapi/qapi-visit-virtio.h" #include "qapi/qmp/qerror.h" #include "qemu/ctype.h" @@ -723,6 +724,19 @@ const PropertyInfo qdev_prop_zero_page_detection =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- SsidSizeMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(SsidSizeMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_ssidsize_mode =3D { + .type =3D "SsidSizeMode", + .description =3D "ssidsize mode: auto, 0-20", + .enum_table =3D &SsidSizeMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index ec21732ce5..4708885164 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -14,6 +14,7 @@ extern const PropertyInfo qdev_prop_multifd_compression; extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; +extern const PropertyInfo qdev_prop_ssidsize_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -61,6 +62,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; #define DEFINE_PROP_ZERO_PAGE_DETECTION(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_zero_page_detection, \ ZeroPageDetection) +#define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index f921d740f1..b372a3661b 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -45,3 +45,18 @@ # { "version": 3, "emulated": false, "kernel": true } = ] } ## { 'command': 'query-gic-capabilities', 'returns': ['GICCapability'] } + +## +# @SsidSizeMode: +# +# SMMUv3 SubstreamID size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# Values 0-20: SSIDSIZE value in bits. 0 disables SubstreamID. +# +# Since: 11.0 +## +{ 'enum': 'SsidSizeMode', + 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2= 0' ] } diff --git a/qapi/pragma.json b/qapi/pragma.json index 193bc39059..24aebbe8f5 100644 --- a/qapi/pragma.json +++ b/qapi/pragma.json @@ -68,6 +68,7 @@ 'S390CpuEntitlement', 'S390CpuPolarization', 'S390CpuState', + 'SsidSizeMode', 'String', 'StringWrapper', 'SysEmuTarget', --=20 2.43.0 From nobody Sat Apr 11 21:30:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= , Alex Williamson , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Eric Blake , Markus Armbruster , Nathan Chen Subject: [RFC PATCH 6/8] hw/arm/smmuv3-accel: Introduce _AUTO support for SSID size Date: Mon, 9 Mar 2026 12:21:17 -0700 Message-ID: <20260309192119.870186-7-nathanc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260309192119.870186-1-nathanc@nvidia.com> References: <20260309192119.870186-1-nathanc@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR08CA0029.namprd08.prod.outlook.com (2603:10b6:a03:100::42) To CY3PR12MB9555.namprd12.prod.outlook.com (2603:10b6:930:10a::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY3PR12MB9555:EE_|DS0PR12MB7852:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b215735-abdf-4a29-42e4-08de7e1134c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|7416014|376014; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084246392154100 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 SSID size property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving SSID size from IDR1. Set the default ssidsize value to auto. The default SSID size used to be 0, but we change it to match what the host IOMMU properties report so that users do not have to introspect host IDR1 for the Substream ID support. When the auto SSID size is resolved to a non-zero value, PASID capability is advertised to the vIOMMU and accelerated use cases such as Shared Virtual Addressing (SVA) are supported. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 30 +++++++++++++++++++++++++++--- hw/arm/smmuv3.c | 16 ++++++---------- include/hw/arm/smmuv3.h | 3 ++- 3 files changed, 35 insertions(+), 14 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 02e3f7a9f3..bd27b0da7c 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -64,6 +64,13 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, FIELD_EX32(info->idr[3], IDR3, RIL)); } =20 + /* Update SSIDSIZE if auto from info */ + if (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + /* Store for get_viommu_flags() to determine PASID support */ + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + FIELD_EX32(info->idr[1], IDR1, SSIDSIZE)); + } + accel->auto_finalised =3D true; } =20 @@ -839,7 +846,10 @@ static uint64_t smmuv3_accel_get_viommu_flags(void *op= aque) SMMUState *bs =3D opaque; SMMUv3State *s =3D ARM_SMMUV3(bs); =20 - if (s->ssidsize) { + if ((s->ssidsize !=3D SSID_SIZE_MODE_0 && + s->ssidsize !=3D SSID_SIZE_MODE_AUTO) || + (s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO && + FIELD_EX32(s->idr[1], IDR1, SSIDSIZE))) { flags |=3D VIOMMU_FLAG_PASID_SUPPORTED; } return flags; @@ -854,6 +864,16 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 +static uint8_t ssidsize_mode_to_value(SsidSizeMode mode) +{ + /* SSID_SIZE_MODE_0 =3D 1, SSID_SIZE_MODE_1 =3D 2, etc. */ + /* SSID_SIZE_MODE_AUTO =3D 0 */ + if (mode =3D=3D SSID_SIZE_MODE_AUTO) { + return 0; + } + return mode - 1; /* Enum values are offset by 1 from actual values */ +} + void smmuv3_accel_idr_override(SMMUv3State *s) { if (!s->accel) { @@ -886,7 +906,10 @@ void smmuv3_accel_idr_override(SMMUv3State *s) * By default QEMU SMMUv3 has no SubstreamID support. Update IDR1 if u= ser * has enabled it. */ - s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, s->ssidsize); + if (s->ssidsize !=3D SSID_SIZE_MODE_AUTO) { + s->idr[1] =3D FIELD_DP32(s->idr[1], IDR1, SSIDSIZE, + ssidsize_mode_to_value(s->ssidsize)); + } } =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ @@ -955,7 +978,8 @@ void smmuv3_accel_init(SMMUv3State *s) smmuv3_accel_as_init(s); =20 if (s->ats =3D=3D ON_OFF_AUTO_AUTO || - s->ril =3D=3D ON_OFF_AUTO_AUTO) { + s->ril =3D=3D ON_OFF_AUTO_AUTO || + s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 7791e5294d..bc03353759 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -20,6 +20,7 @@ #include "qemu/bitops.h" #include "hw/core/irq.h" #include "hw/core/sysbus.h" +#include "hw/core/qdev-properties-system.h" #include "migration/blocker.h" #include "migration/vmstate.h" #include "hw/core/qdev-properties.h" @@ -626,7 +627,7 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg, } =20 /* Multiple context descriptors require SubstreamID support */ - if (!s->ssidsize && STE_S1CDMAX(ste) !=3D 0) { + if (s->ssidsize =3D=3D SSID_SIZE_MODE_0 && STE_S1CDMAX(ste) !=3D 0) { qemu_log_mask(LOG_UNIMP, "SMMUv3: multiple S1 context descriptors require Substream= ID support. " "Configure ssidsize > 0 (requires accel=3Don)\n"); @@ -1985,7 +1986,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } - if (s->ssidsize) { + if (s->ssidsize > SSID_SIZE_MODE_0) { error_setg(errp, "ssidsize can only be set if accel=3Don"); return false; } @@ -2003,11 +2004,6 @@ static bool smmu_validate_property(SMMUv3State *s, E= rror **errp) error_setg(errp, "OAS can only be set to 44 or 48 bits"); return false; } - if (s->ssidsize > SMMU_SSID_MAX_BITS) { - error_setg(errp, "ssidsize must be in the range 0 to %d", - SMMU_SSID_MAX_BITS); - return false; - } =20 return true; } @@ -2136,7 +2132,8 @@ static const Property smmuv3_properties[] =3D { DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), - DEFINE_PROP_UINT8("ssidsize", SMMUv3State, ssidsize, 0), + DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, + SSID_SIZE_MODE_AUTO), }; =20 static void smmuv3_instance_init(Object *obj) @@ -2176,8 +2173,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " "Valid range is 0-20, where 0 disables SubstreamID support. " - "Defaults to 0. A value greater than 0 is required to enable " - "PASID support."); + "A value greater than 0 is required to enable PASID support."); } =20 static int smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index 9124bfe751..ae8158a5c3 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -21,6 +21,7 @@ =20 #include "hw/arm/smmu-common.h" #include "qom/object.h" +#include "qapi/qapi-types-misc-arm.h" =20 #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" =20 @@ -72,7 +73,7 @@ struct SMMUv3State { OnOffAuto ril; OnOffAuto ats; uint8_t oas; - uint8_t ssidsize; + SsidSizeMode ssidsize; }; =20 typedef enum { --=20 2.43.0 From nobody Sat Apr 11 21:30:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=nvidia.com); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084306503158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Introduce a new enum type property allowing to set an Output Address Size. Values are auto, 44, and 48, where a value of N specifies an N-bit OAS. Signed-off-by: Nathan Chen --- hw/core/qdev-properties-system.c | 13 +++++++++++++ include/hw/core/qdev-properties-system.h | 3 +++ qapi/misc-arm.json | 16 ++++++++++++++++ 3 files changed, 32 insertions(+) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-sys= tem.c index 4aca1d4326..a805ee2e1f 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -737,6 +737,19 @@ const PropertyInfo qdev_prop_ssidsize_mode =3D { .set_default_value =3D qdev_propinfo_set_default_value_enum, }; =20 +/* --- OasMode --- */ + +QEMU_BUILD_BUG_ON(sizeof(OasMode) !=3D sizeof(int)); + +const PropertyInfo qdev_prop_oas_mode =3D { + .type =3D "OasMode", + .description =3D "oas mode: auto, 32, 36, 40, 42, 44, 48, 52, 56", + .enum_table =3D &OasMode_lookup, + .get =3D qdev_propinfo_get_enum, + .set =3D qdev_propinfo_set_enum, + .set_default_value =3D qdev_propinfo_set_default_value_enum, +}; + /* --- Reserved Region --- */ =20 /* diff --git a/include/hw/core/qdev-properties-system.h b/include/hw/core/qde= v-properties-system.h index 4708885164..2cbea16d61 100644 --- a/include/hw/core/qdev-properties-system.h +++ b/include/hw/core/qdev-properties-system.h @@ -15,6 +15,7 @@ extern const PropertyInfo qdev_prop_mig_mode; extern const PropertyInfo qdev_prop_granule_mode; extern const PropertyInfo qdev_prop_zero_page_detection; extern const PropertyInfo qdev_prop_ssidsize_mode; +extern const PropertyInfo qdev_prop_oas_mode; extern const PropertyInfo qdev_prop_losttickpolicy; extern const PropertyInfo qdev_prop_blockdev_on_error; extern const PropertyInfo qdev_prop_bios_chs_trans; @@ -64,6 +65,8 @@ extern const PropertyInfo qdev_prop_virtio_gpu_output_lis= t; ZeroPageDetection) #define DEFINE_PROP_SSIDSIZE_MODE(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_ssidsize_mode, SsidSizeMo= de) +#define DEFINE_PROP_OAS_MODE(_n, _s, _f, _d) \ + DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_oas_mode, OasMode) #define DEFINE_PROP_LOSTTICKPOLICY(_n, _s, _f, _d) \ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_losttickpolicy, \ LostTickPolicy) diff --git a/qapi/misc-arm.json b/qapi/misc-arm.json index b372a3661b..76b6965502 100644 --- a/qapi/misc-arm.json +++ b/qapi/misc-arm.json @@ -60,3 +60,19 @@ { 'enum': 'SsidSizeMode', 'data': [ 'auto', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', '10', '11', '12', '13', '14', '15', '16', '17', '18', '19', '2= 0' ] } + +## +# @OasMode: +# +# SMMUv3 Output Address Size configuration mode. +# +# @auto: derive from host IOMMU capabilities +# +# @44: 44-bit output address size +# +# @48: 48-bit output address size +# +# Since: 11.0 +## +{ 'enum': 'OasMode', + 'data': [ 'auto', '44', '48' ] } --=20 2.43.0 From nobody Sat Apr 11 21:30:50 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: permerror client-ip=2a01:111:f403:c110::3; envelope-from=nathanc@nvidia.com; helo=BN8PR05CU002.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1773084326617158500 Content-Type: text/plain; charset="utf-8" From: Nathan Chen Allow accelerated SMMUv3 OAS property to be derived from host IOMMU capabilities. Derive host values using IOMMU_GET_HW_INFO, retrieving OAS from IDR5. Set the default oas value to auto. The default Output Address Size used to be 44-bit, but we change it to match what the host IOMMU properties report so that users do not have to introspect host IDR5 for the OAS. This keeps the OAS value advertised by the virtual SMMU compatible with the capabilities of the host SMMUv3, so that the intermediate physical addresses (IPA) consumed by host SMMU for stage-2 translation do not exceed the host's max supported IPA size. Signed-off-by: Nathan Chen --- hw/arm/smmuv3-accel.c | 11 +++++++++-- hw/arm/smmuv3.c | 11 ++++++----- include/hw/arm/smmuv3.h | 2 +- 3 files changed, 16 insertions(+), 8 deletions(-) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index bd27b0da7c..03950a4cef 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -71,6 +71,12 @@ static void smmuv3_accel_auto_finalise(SMMUv3State *s, P= CIDevice *pdev, FIELD_EX32(info->idr[1], IDR1, SSIDSIZE)); } =20 + /* Update OAS if auto from info */ + if (s->oas =3D=3D OAS_MODE_AUTO) { + s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, + FIELD_EX32(info->idr[5], IDR5, OAS)); + } + accel->auto_finalised =3D true; } =20 @@ -898,7 +904,7 @@ void smmuv3_accel_idr_override(SMMUv3State *s) } =20 /* Advertise 48-bit OAS in IDR5 when requested (default is 44 bits). */ - if (s->oas =3D=3D SMMU_OAS_48BIT) { + if (s->oas =3D=3D OAS_MODE_48) { s->idr[5] =3D FIELD_DP32(s->idr[5], IDR5, OAS, SMMU_IDR5_OAS_48); } =20 @@ -979,7 +985,8 @@ void smmuv3_accel_init(SMMUv3State *s) =20 if (s->ats =3D=3D ON_OFF_AUTO_AUTO || s->ril =3D=3D ON_OFF_AUTO_AUTO || - s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO) { + s->ssidsize =3D=3D SSID_SIZE_MODE_AUTO || + s->oas =3D=3D OAS_MODE_AUTO) { s->s_accel->auto_mode =3D true; } } diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index bc03353759..4fc4ed2c06 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1982,7 +1982,7 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) error_setg(errp, "ats can only be enabled if accel=3Don"); return false; } - if (s->oas !=3D SMMU_OAS_44BIT) { + if (s->oas > OAS_MODE_44) { error_setg(errp, "OAS must be 44 bits when accel=3Doff"); return false; } @@ -2000,8 +2000,9 @@ static bool smmu_validate_property(SMMUv3State *s, Er= ror **errp) return false; } =20 - if (s->oas !=3D SMMU_OAS_44BIT && s->oas !=3D SMMU_OAS_48BIT) { - error_setg(errp, "OAS can only be set to 44 or 48 bits"); + if (s->oas !=3D OAS_MODE_AUTO && s->oas !=3D OAS_MODE_44 && + s->oas !=3D OAS_MODE_48) { + error_setg(errp, "OAS can only be set to auto, 44 bits, or 48 bits= "); return false; } =20 @@ -2131,7 +2132,7 @@ static const Property smmuv3_properties[] =3D { /* RIL can be turned off for accel cases */ DEFINE_PROP_ON_OFF_AUTO("ril", SMMUv3State, ril, ON_OFF_AUTO_AUTO), DEFINE_PROP_ON_OFF_AUTO("ats", SMMUv3State, ats, ON_OFF_AUTO_AUTO), - DEFINE_PROP_UINT8("oas", SMMUv3State, oas, 44), + DEFINE_PROP_OAS_MODE("oas", SMMUv3State, oas, OAS_MODE_AUTO), DEFINE_PROP_SSIDSIZE_MODE("ssidsize", SMMUv3State, ssidsize, SSID_SIZE_MODE_AUTO), }; @@ -2168,7 +2169,7 @@ static void smmuv3_class_init(ObjectClass *klass, con= st void *data) "platform has ATS support before enabling this"); object_class_property_set_description(klass, "oas", "Specify Output Address Size (for accel=3Don). Supported values " - "are 44 or 48 bits. Defaults to 44 bits"); + "are 44 or 48 bits."); object_class_property_set_description(klass, "ssidsize", "Number of bits used to represent SubstreamIDs (SSIDs). " "A value of N allows SSIDs in the range [0 .. 2^N - 1]. " diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index ae8158a5c3..3bfee63396 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -72,7 +72,7 @@ struct SMMUv3State { Error *migration_blocker; OnOffAuto ril; OnOffAuto ats; - uint8_t oas; + OasMode oas; SsidSizeMode ssidsize; }; =20 --=20 2.43.0