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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.79.5; envelope-from=mohamed@unpredictable.fr; helo=outbound.st.icloud.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.819, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.903, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1773056911519158500 Apple headers say: > When EL2 is disabled, PMU register accesses trigger "Trapped MSR, MRS, or > System Instruction" exceptions. When this happens, hv_vcpu_run()=E2=80=AF= returns, and the > =E2=80=AFhv_vcpu_exit_t=E2=80=AFobject contains the information about thi= s exception. > When EL2 is enabled, the handling of PMU register accesses is determined = by the PMUVer > field of ID_AA64DFR0_EL1=E2=80=AFregister. > If the PMUVer=E2=80=AFfield value is zero or is invalid, PMU register acc= esses generate "Undefined" > exceptions, which are sent to the guest. > If the PMUVer=E2=80=AFfield value is non-zero and valid, PMU register acc= esses are emulated by the framework. > The ID_AA64DFR0_EL1=E2=80=AFregister can be modified via hv_vcpu_set_sys_= reg=E2=80=AFAPI. That documentation turns out to not be so accurate, with the determining fa= ctor being whether the vGIC is enabled instead of nested virtualisation. If ID_AA64DFR0_EL1.PMUVer =3D = 0, Hypervisor.framework doesn't give us the luxury of having PMU sysreg accesses trapped to the VMM when th= e vGIC is enabled. As Windows really wants at least a single counter PMU, give it even when using the kernel-irqchip with nested virt off. Signed-off-by: Mohamed Mediouni --- target/arm/hvf/hvf.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8aa59a1f77..136761b429 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1187,8 +1187,12 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPU= Features *ahcf) =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 - if (hvf_nested_virt_enabled()) { + /* Windows really wants at least a single counter PMU... */ + if (hvf_irqchip_in_kernel()) { FIELD_DP64_IDREG(&host_isar, ID_AA64DFR0, PMUVER, 0x1); + } + + if (hvf_nested_virt_enabled()) { /* SME is not implemented with nested virt on the Apple side */ FIELD_DP64_IDREG(&host_isar, ID_AA64PFR1, SME, 0); } @@ -1660,7 +1664,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; =20 - if (!hvf_nested_virt_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_irqchip_in_kernel() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCR_EL0: *val =3D env->cp15.c9_pmcr; @@ -1930,7 +1934,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) SYSREG_OP2(reg), val); =20 - if (!hvf_nested_virt_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_irqchip_in_kernel() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCCNTR_EL0: pmu_op_start(env); --=20 2.50.1 (Apple Git-155)