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Sun, 08 Mar 2026 15:39:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 43/49] hppa: Get physical address space bits from HPPACPUDef Date: Sun, 8 Mar 2026 23:34:27 +0100 Message-ID: <20260308223433.25503-44-philmd@linaro.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260308223433.25503-1-philmd@linaro.org> References: <20260308223433.25503-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1773009582756154100 From: Anton Johansson Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20260305-hppa-c3600-v6-2-d51526e5269c@rev.ng> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci-host/astro.h | 2 ++ target/hppa/cpu.h | 11 ++++++++--- hw/hppa/machine.c | 15 +++++++++----- hw/pci-host/astro.c | 8 +++++++- target/hppa/cpu.c | 5 +++++ target/hppa/mem_helper.c | 39 +++++++++++-------------------------- 6 files changed, 43 insertions(+), 37 deletions(-) diff --git a/include/hw/pci-host/astro.h b/include/hw/pci-host/astro.h index 832125a05af..fce052c9f86 100644 --- a/include/hw/pci-host/astro.h +++ b/include/hw/pci-host/astro.h @@ -82,6 +82,8 @@ struct AstroState { uint64_t tlb_tcnfg; uint64_t tlb_pdir_base; =20 + uint8_t phys_addr_bits; + struct ElroyState *elroy[ELROY_NUM]; =20 MemoryRegion this_mem; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 43b4882fb4f..7d47afe8efa 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -320,6 +320,11 @@ static inline const HPPACPUDef *hppa_def(CPUHPPAState = *env) return HPPA_CPU_GET_CLASS(env_cpu(env))->def; } =20 +static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) +{ + return hppa_def(env)->phys_addr_bits; +} + static inline bool hppa_is_pa20(CPUHPPAState *env) { return hppa_def(env)->is_pa20; @@ -352,9 +357,9 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 -hwaddr hppa_abs_to_phys_pa1x(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); +hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr); =20 /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 5d0d4de09ed..6b69a304c2a 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -179,19 +179,21 @@ static uint64_t linux_kernel_virt_to_phys(void *opaqu= e, uint64_t addr) return addr; } =20 +static HPPACPU *cpu[HPPA_MAX_CPUS]; +static uint64_t firmware_entry; + static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa1x(addr); + const uint8_t pa_bits =3D hppa_phys_addr_bits(&cpu[0]->env); + return hppa_abs_to_phys_pa1x(pa_bits, addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa2_w0(addr); + const uint8_t pa_bits =3D hppa_phys_addr_bits(&cpu[0]->env); + return hppa_abs_to_phys_pa2_w0(pa_bits, addr); } =20 -static HPPACPU *cpu[HPPA_MAX_CPUS]; -static uint64_t firmware_entry; - static void fw_cfg_boot_set(void *opaque, const char *boot_device, Error **errp) { @@ -685,6 +687,9 @@ static AstroState *astro_init(void) DeviceState *dev; =20 dev =3D qdev_new(TYPE_ASTRO_CHIP); + object_property_set_int(OBJECT(dev), "phys-addr-bits", + hppa_phys_addr_bits(&cpu[0]->env), + &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 return ASTRO_CHIP(dev); diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 00a904277c0..626aa9ce223 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -303,7 +303,7 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryR= egion *iommu, * language which not-coincidentally matches the PSW.W=3D0 mapping. */ if (addr <=3D UINT32_MAX) { - entry =3D hppa_abs_to_phys_pa2_w0(addr); + entry =3D hppa_abs_to_phys_pa2_w0(s->phys_addr_bits, addr); } else { entry =3D addr; } @@ -910,6 +910,10 @@ static void astro_realize(DeviceState *obj, Error **er= rp) } } =20 +static const Property astro_props[] =3D { + DEFINE_PROP_UINT8("phys-addr-bits", AstroState, phys_addr_bits, 32), +}; + static void astro_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -922,6 +926,8 @@ static void astro_class_init(ObjectClass *klass, const = void *data) * be created without that hardware */ dc->user_creatable =3D false; + + device_class_set_props(dc, astro_props); } =20 static const TypeInfo astro_chip_info =3D { diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cc755da8be2..5895b9d7c09 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -283,6 +283,11 @@ static void hppa_cpu_class_base_init(ObjectClass *oc, = const void *data) /* Make sure all CPU models define a HPPACPUDef */ g_assert(!object_class_is_abstract(oc) && data !=3D NULL); acc->def =3D data; + /* + * Verify assumptions made in hppa_abs_to_phys_pa2_w1() on the size + * of the physical address space. + */ + g_assert(acc->def->phys_addr_bits <=3D 54); } =20 static void hppa_cpu_class_init(ObjectClass *oc, const void *data) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9199d1e06ab..a4b382069d8 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,29 +29,12 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -/* - * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit - * machines 7300LC. This should give 44 and 32 bits of physical address - * space respectively. - * - * CPU model Physical address space bits - * PA-7000--7300LC 32 - * PA-8000--8600 40 - * PA-8700--8900 44 - * - * FIXME: However, the SeaBIOS firmware that is that tested against - * uses 40-bit physical addresses, despite supposedly running a C3700 - * with a PA-8700 cpu, so use 40-bits for 64-bit. - */ -#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 -#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 - -hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr) { - return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); + return extract64(addr, 0, phys_addr_bits); } =20 -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr) { /* * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes @@ -64,11 +47,10 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); - return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + return sextract64(addr, 0, phys_addr_bits); } =20 -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr) { /* * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", @@ -89,7 +71,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); + addr |=3D -1ull << (phys_addr_bits - 4); } return addr; } @@ -231,15 +213,16 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, =20 /* Virtual translation disabled. Map absolute to physical. */ if (MMU_IDX_MMU_DISABLED(mmu_idx)) { + const uint8_t phys_addr_bits =3D hppa_phys_addr_bits(env); switch (mmu_idx) { case MMU_ABS_W_IDX: - phys =3D hppa_abs_to_phys_pa2_w1(addr); + phys =3D hppa_abs_to_phys_pa2_w1(phys_addr_bits, addr); break; case MMU_ABS_IDX: if (hppa_is_pa20(env)) { - phys =3D hppa_abs_to_phys_pa2_w0(addr); + phys =3D hppa_abs_to_phys_pa2_w0(phys_addr_bits, addr); } else { - phys =3D hppa_abs_to_phys_pa1x(addr); + phys =3D hppa_abs_to_phys_pa1x(phys_addr_bits, addr); } break; default: @@ -580,7 +563,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + ent->pa =3D sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.53.0