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These registers are also updated when the src and/or dst clipping fields on DP_GUI_MASTER_CNTL are set to default clipping. Scissor clipping is used when rendering text in X.org. The r128 driver sends host data much wider than is necessary to draw a glyph and cuts it down to size using clipping before rendering. The actual clipping implementation follows in a future patch. This also includes a very minor refactor of the combined default_sc_bottom_right field in the registers struct to default_sc_bottom and default_sc_right. This was done to stay consistent with the other scissor registers and prevent repeated masking and extraction. Signed-off-by: Chad Jablonski Reviewed-by: BALATON Zoltan Message-ID: <20260303024730.1489136-7-chad@jablonski.xyz> Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/display/ati_int.h | 9 +++++- hw/display/ati_regs.h | 2 ++ hw/display/ati.c | 70 +++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 78 insertions(+), 3 deletions(-) diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 708cc1dd3a3..98f57ca5fa4 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -78,14 +78,21 @@ typedef struct ATIVGARegs { uint32_t dp_brush_frgd_clr; uint32_t dp_src_frgd_clr; uint32_t dp_src_bkgd_clr; + uint16_t sc_top; + uint16_t sc_left; + uint16_t sc_bottom; + uint16_t sc_right; + uint16_t src_sc_bottom; + uint16_t src_sc_right; uint32_t dp_cntl; uint32_t dp_datatype; uint32_t dp_mix; uint32_t dp_write_mask; uint32_t default_offset; uint32_t default_pitch; + uint16_t default_sc_bottom; + uint16_t default_sc_right; uint32_t default_tile; - uint32_t default_sc_bottom_right; } ATIVGARegs; =20 struct ATIVGAState { diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 0a0825db048..3999edb9b71 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -397,6 +397,8 @@ #define GMC_DST_PITCH_OFFSET_CNTL 0x00000002 #define GMC_SRC_CLIP_DEFAULT 0x00000000 #define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIPPING 0x00000004 +#define GMC_DST_CLIPPING 0x00000008 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 #define GMC_SRC_DSTCOLOR 0x00003000 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 diff --git a/hw/display/ati.c b/hw/display/ati.c index 26fc74b19b3..6cf243bcf95 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -514,7 +514,32 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr,= unsigned int size) val |=3D s->regs.default_tile << 16; break; case DEFAULT_SC_BOTTOM_RIGHT: - val =3D s->regs.default_sc_bottom_right; + val =3D (s->regs.default_sc_bottom << 16) | + s->regs.default_sc_right; + break; + case SC_TOP: + val =3D s->regs.sc_top; + break; + case SC_LEFT: + val =3D s->regs.sc_left; + break; + case SC_BOTTOM: + val =3D s->regs.sc_bottom; + break; + case SC_RIGHT: + val =3D s->regs.sc_right; + break; + case SRC_SC_BOTTOM: + val =3D s->regs.src_sc_bottom; + break; + case SRC_SC_RIGHT: + val =3D s->regs.src_sc_right; + break; + case SC_TOP_LEFT: + case SC_BOTTOM_RIGHT: + case SRC_SC_BOTTOM_RIGHT: + qemu_log_mask(LOG_GUEST_ERROR, + "Read from write-only register 0x%x\n", (unsigned)ad= dr); break; default: break; @@ -877,6 +902,16 @@ static void ati_mm_write(void *opaque, hwaddr addr, s->regs.dst_offset =3D s->regs.default_offset; s->regs.dst_pitch =3D s->regs.default_pitch; } + if (!(data & GMC_SRC_CLIPPING)) { + s->regs.src_sc_right =3D s->regs.default_sc_right; + s->regs.src_sc_bottom =3D s->regs.default_sc_bottom; + } + if (!(data & GMC_DST_CLIPPING)) { + s->regs.sc_top =3D 0; + s->regs.sc_left =3D 0; + s->regs.sc_right =3D s->regs.default_sc_right; + s->regs.sc_bottom =3D s->regs.default_sc_bottom; + } break; case DST_WIDTH_X: s->regs.dst_x =3D data & 0x3fff; @@ -956,7 +991,38 @@ static void ati_mm_write(void *opaque, hwaddr addr, } break; case DEFAULT_SC_BOTTOM_RIGHT: - s->regs.default_sc_bottom_right =3D data & 0x3fff3fff; + s->regs.default_sc_right =3D data & 0x3fff; + s->regs.default_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_TOP_LEFT: + s->regs.sc_left =3D data & 0x3fff; + s->regs.sc_top =3D (data >> 16) & 0x3fff; + break; + case SC_LEFT: + s->regs.sc_left =3D data & 0x3fff; + break; + case SC_TOP: + s->regs.sc_top =3D data & 0x3fff; + break; + case SC_BOTTOM_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + s->regs.sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SC_RIGHT: + s->regs.sc_right =3D data & 0x3fff; + break; + case SC_BOTTOM: + s->regs.sc_bottom =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + s->regs.src_sc_bottom =3D (data >> 16) & 0x3fff; + break; + case SRC_SC_RIGHT: + s->regs.src_sc_right =3D data & 0x3fff; + break; + case SRC_SC_BOTTOM: + s->regs.src_sc_bottom =3D data & 0x3fff; break; default: break; --=20 2.53.0