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Tsirkin" , Igor Mammedov , =?UTF-8?q?Cl=C3=A9ment=20Mathieu--Drif?= , Paolo Bonzini , Stefan Berger , Ani Sinha , Thomas Huth Subject: [PATCH 07/10] target/i386/cpu: Remove X86CPU::intel_pt_auto_level field Date: Sat, 7 Mar 2026 16:26:31 +0100 Message-ID: <20260307152635.83893-8-philmd@linaro.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260307152635.83893-1-philmd@linaro.org> References: <20260307152635.83893-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772897267788154100 The X86CPU::intel_pt_auto_level boolean was only set in the pc_compat_3_1[] array, via the 'x-intel-pt-auto-level=3Doff' property. We removed all machines using that array, lets remove that property and all the code around it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/i386/cpu.h | 3 --- target/i386/cpu.c | 8 -------- 2 files changed, 11 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 2b70d56e9b0..5a62aa61579 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2457,9 +2457,6 @@ struct ArchCPU { /* Only advertise TOPOEXT features that AMD defines */ bool amd_topoext_features_only; =20 - /* Enable auto level-increase for Intel Processor Trace leave */ - bool intel_pt_auto_level; - /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ bool fill_mtrr_mask; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c77addd2c25..d8cd0d81d7f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9565,13 +9565,7 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) =20 /* Intel Processor Trace requires CPUID[0x14] */ if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { - if (cpu->intel_pt_auto_level) { x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); - } else if (cpu->env.cpuid_min_level < 0x14) { - mark_unavailable_features(cpu, FEAT_7_0_EBX, - CPUID_7_0_EBX_INTEL_PT, - "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,i= ntel-pt=3Don,min-level=3D0x14\""); - } } =20 /* @@ -10589,8 +10583,6 @@ static const Property x86_cpu_properties[] =3D { * to the specific Windows version being used." */ DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1), - DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, - true), DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, t= rue), DEFINE_PROP_BOOL("x-force-cpuid-0x1f", X86CPU, force_cpuid_0x1f, false= ), =20 --=20 2.52.0