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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4853252cae1sm13462255e9.3.2026.03.07.03.29.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Mar 2026 03:29:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1772882974; x=1773487774; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uMhouh8lU7AhEzD5xKxFtylYc2aC2/dOO3bXKq0ZJng=; b=IujCuo3EWmdhwRTjV67A5sqJGhUoAvLCP4luB3XICghIxuidGCZhKFK49MU91fKgbr EfObkU618z5Wsftr8g/00hhOt6X1SySScgWbfUQX5XdmkpiRPDLvOl+DZTWdcTmEgtPv ZG6kzhDPCQwFhDv8sV3klgmKWtyphgCQtgdsISzR3hjtox1Kfzho6JsWU2LOqElH6dWr 9d82xpZatxL96k+af8W/btN/OswZSYsoJ35m3lYEVmXc8yRnw2DjUFb35bLFIbpKX1rK XrptkG1B+kNrQ1YQT/i+m3shfq1O+wDD0yiDELy2KA3hk/NGuID3m4qF+E5B6gqleRxx p3Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772882974; x=1773487774; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=uMhouh8lU7AhEzD5xKxFtylYc2aC2/dOO3bXKq0ZJng=; b=vBT/fDpU8ch7I60NfMcXG1mGfdRbs/h60eEZAL9beIjGUvSDL14R24GGtNuTUCsWgE /7bof9wE/J7NsTVI8IGWomP0bglal2O55Cd7CpfdxGud9VXwesQLI1W1JlvNmRYXs2F3 QWMHuLJifDrA4YOMSo5DeOoYejO0KW3juVyBDPQxmmICFYkyw7+tF849mX26C+nisCtE 2oM6m7g1VKdB2WG1GJc2d9P52q7ITXqV55oDj8oi90fusWEjLu6nEmWCnnSaRjAvASyq ZJXQfgo4zAnJMhLJxeAp97imaXKHLMp3dsyGPQkmqWSOMi53cfiooyrnLL0GOErFMsF2 OZ+w== X-Gm-Message-State: AOJu0YxBjkhG0O952xnMPFHsXHyeCW2QST48GUwUr7AAUgHDtDbPErEv SkdP8DvzRYUHDWWqY7RgKgHHIX9Zb1wPJR4Uraveih07iKLKX35ZTEcC2y4SzMYkR0BHtHxd3GY 1cuex X-Gm-Gg: ATEYQzzUgA6ZRaIoqanSmnorWJyAo61CAGQrP+nPHHafFB4mWc41umVVTSdMHobBaIk SwTwyPQKnMVklsvzaQ7wYeZCdm80g15z94M5AHv/BaJa6fduWrX+8JVcIupS3P1HO81CQ4i4UlE +u39ZZHXIUzHkkAqwtZ6OMlNm/Ybx+3BVp4MyrTLkIunFtWG9NPpNMV610Og08WXkBODdFDQzWK qJ3UZTBrwmcLSPrVWtAS2PGy0BQhvEnUrLu0Xu3jcByrLxmxNtERqGNF2RvvVwZHJlPAjB7/2Gj okw/mwfL1oFU7Kbs2qhyfI12LkEMXHZPn8mnLw7ucs1smZVtwgCm6p0dVjaNeQi5RUHiRvDxUeY IFMIyL8WBY9M6445bte+lgTNV7KFDBl9wU4alGm0m99zEGsprnIaB7N1JTYnijpdjS2g8nxI263 VTxtACeW2FxPJQZ39YGVtE9OyHUs0PauUEPdt2E15d68mkgRu+NbH0fO18UMYrBGubOSSoxPawE he4s37cZnjB9l5LFhhoCmUfeRlQk7U= X-Received: by 2002:a05:600c:1e88:b0:477:6d96:b3e5 with SMTP id 5b1f17b1804b1-48526916beamr101336255e9.7.1772882974219; Sat, 07 Mar 2026 03:29:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 1/3] hw/sparc/sun4m: Don't set up dummy cpu interrupts Date: Sat, 7 Mar 2026 11:29:29 +0000 Message-ID: <20260307112931.3322532-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260307112931.3322532-1-peter.maydell@linaro.org> References: <20260307112931.3322532-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772883026199158500 Content-Type: text/plain; charset="utf-8" In the sun4m machine init, we set up the cpu_irqs[] array with the real inbound IRQs for each CPU, followed by some dummy IRQs for the remaining slots from smp_cpus up to MAX_CPUS. These dummy IRQs do nothing when set/cleared because the dummy_cpu_set_irq() function does nothing. Instead of creating these "do nothing" qemu_irqs, instead pass the number of CPUs to slavio_intctl_init() so that it can only wire up the interrupt controller's interrupts for the CPUs that actually exist. Calling qemu_set_irq() on an irq that isn't connected does nothing, so this is a simpler way to achieve the same result. This cleanup fixes an unimportant memory leak reported by the address sanitizer that happens because we allocate these dummy IRQs with qemu_allocate_irqs(): Direct leak of 1920 byte(s) in 15 object(s) allocated from: #0 0x5cb7b120cf63 in malloc (/home/pm215/qemu/build/san/qemu-system-spa= rc+0xe0bf63) (BuildId: d27f9230a7cc82ebfaf0cf9e439dc215ddd7ac68) #1 0x743cd6dc5ac9 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0= x62ac9) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x5cb7b1a42fb4 in qemu_extend_irqs /home/pm215/qemu/build/san/../../= hw/core/irq.c:77:51 #3 0x5cb7b19e7e72 in sun4m_hw_init /home/pm215/qemu/build/san/../../hw/= sparc/sun4m.c:845:23 #4 0x5cb7b141d3dd in machine_run_board_init /home/pm215/qemu/build/san/= ../../hw/core/machine.c:1709:5 #5 0x5cb7b1542895 in qemu_init_board /home/pm215/qemu/build/san/../../s= ystem/vl.c:2717:5 #6 0x5cb7b1542895 in qmp_x_exit_preconfig /home/pm215/qemu/build/san/..= /../system/vl.c:2811:5 #7 0x5cb7b15493ac in qemu_init /home/pm215/qemu/build/san/../../system/= vl.c:3849:9 #8 0x5cb7b1f3f201 in main /home/pm215/qemu/build/san/../../system/main.= c:71:5 #9 0x743cd4a2a1c9 in __libc_start_call_main csu/../sysdeps/nptl/libc_st= art_call_main.h:58:16 #10 0x743cd4a2a28a in __libc_start_main csu/../csu/libc-start.c:360:3 #11 0x5cb7b1172114 in _start (/home/pm215/qemu/build/san/qemu-system-sp= arc+0xd71114) (BuildId: d27f9230a7cc82ebfaf0cf9e439dc215ddd7ac68) Signed-off-by: Peter Maydell Reviewed-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index a17bdb3692..29bc26ebcb 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -196,10 +196,6 @@ static void cpu_set_irq(void *opaque, int irq, int lev= el) } } =20 -static void dummy_cpu_set_irq(void *opaque, int irq, int level) -{ -} - static void sun4m_cpu_reset(void *opaque) { SPARCCPU *cpu =3D opaque; @@ -344,6 +340,7 @@ static void *sparc32_dma_init(hwaddr dma_base, =20 static DeviceState *slavio_intctl_init(hwaddr addr, hwaddr addrg, + unsigned int smp_cpus, qemu_irq **parent_irq) { DeviceState *dev; @@ -355,7 +352,7 @@ static DeviceState *slavio_intctl_init(hwaddr addr, s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); =20 - for (i =3D 0; i < MAX_CPUS; i++) { + for (i =3D 0; i < smp_cpus; i++) { for (j =3D 0; j < MAX_PILS; j++) { sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); } @@ -841,9 +838,6 @@ static void sun4m_hw_init(MachineState *machine) cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]= ); } =20 - for (i =3D smp_cpus; i < MAX_CPUS; i++) - cpu_irqs[i] =3D qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PI= LS); - /* Create and map RAM frontend */ dev =3D qdev_new("memory"); object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &e= rror_fatal); @@ -860,6 +854,7 @@ static void sun4m_hw_init(MachineState *machine) =20 slavio_intctl =3D slavio_intctl_init(hwdef->intctl_base, hwdef->intctl_base + 0x10000ULL, + smp_cpus, cpu_irqs); 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This results in a memory leak: Direct leak of 128 byte(s) in 1 object(s) allocated from: #0 0x5a23c1281ec3 in malloc (/home/pm215/qemu/build/sparc-san/qemu-syst= em-sparc+0xdf1ec3) (BuildId: e6aa10be01feb5524656dd083997bc82b85e3e93) #1 0x79e8f78f0ac9 in g_malloc (/lib/x86_64-linux-gnu/libglib-2.0.so.0+0= x62ac9) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x5a23c1a94e54 in qemu_extend_irqs /home/pm215/qemu/build/sparc-san/= ../../hw/core/irq.c:77:51 #3 0x5a23c1a39e03 in cpu_devinit /home/pm215/qemu/build/sparc-san/../..= /hw/sparc/sun4m.c:802:17 #4 0x5a23c1a39e03 in sun4m_hw_init /home/pm215/qemu/build/sparc-san/../= ../hw/sparc/sun4m.c:838:9 The leak is unimportant as it is a "once at startup" leak, but fixing it helps in getting a clean leak-sanitizer test run. Switch the sun4m code to handle CPU interrupt lines in the same way as the leon3 machine does: the machine init code uses qdev_init_gpio_in to create GPIO lines on the CPU objects. This is a little bit odd as ideally the CPU would do that itself, but for these 32-bit SPARC machines the machine and the CPU are very closely coupled already (the functions handling the IRQ lines modify data fields inside the CPU). Signed-off-by: Peter Maydell Reviewed-by: Mark Cave-Ayland --- hw/sparc/sun4m.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 29bc26ebcb..b9f8236be5 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -341,7 +341,7 @@ static void *sparc32_dma_init(hwaddr dma_base, static DeviceState *slavio_intctl_init(hwaddr addr, hwaddr addrg, unsigned int smp_cpus, - qemu_irq **parent_irq) + DeviceState **cpus) { DeviceState *dev; SysBusDevice *s; @@ -354,7 +354,8 @@ static DeviceState *slavio_intctl_init(hwaddr addr, =20 for (i =3D 0; i < smp_cpus; i++) { for (j =3D 0; j < MAX_PILS; j++) { - sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); + sysbus_connect_irq(s, i * MAX_PILS + j, + qdev_get_gpio_in_named(cpus[i], "pil", j)); } } sysbus_mmio_map(s, 0, addrg); @@ -785,22 +786,25 @@ static const TypeInfo ram_info =3D { .class_init =3D ram_class_init, }; =20 -static void cpu_devinit(const char *cpu_type, unsigned int id, - uint64_t prom_addr, qemu_irq **cpu_irqs) +static DeviceState *cpu_devinit(const char *cpu_type, unsigned int id, + uint64_t prom_addr) { SPARCCPU *cpu; CPUSPARCState *env; + DeviceState *cpudev; =20 cpu =3D SPARC_CPU(object_new(cpu_type)); env =3D &cpu->env; + cpudev =3D DEVICE(cpu); =20 qemu_register_reset(sun4m_cpu_reset, cpu); object_property_set_bool(OBJECT(cpu), "start-powered-off", id !=3D 0, &error_abort); - qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + qdev_init_gpio_in_named(cpudev, cpu_set_irq, "pil", MAX_PILS); + qdev_realize_and_unref(cpudev, NULL, &error_fatal); cpu_sparc_set_id(env, id); - *cpu_irqs =3D qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); env->prom_addr =3D prom_addr; + return cpudev; } =20 static void dummy_fdc_tc(void *opaque, int irq, int level) @@ -813,13 +817,14 @@ static void sun4m_hw_init(MachineState *machine) DeviceState *slavio_intctl; unsigned int i; Nvram *nvram; - qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; + qemu_irq slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; qemu_irq fdc_tc; unsigned long kernel_size; uint32_t initrd_size; DriveInfo *fd[MAX_FD]; FWCfgState *fw_cfg; DeviceState *dev, *ms_kb_orgate, *serial_orgate; + DeviceState *cpus[MAX_CPUS]; SysBusDevice *s; unsigned int smp_cpus =3D machine->smp.cpus; unsigned int max_cpus =3D machine->smp.max_cpus; @@ -835,7 +840,7 @@ static void sun4m_hw_init(MachineState *machine) =20 /* init CPUs */ for(i =3D 0; i < smp_cpus; i++) { - cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]= ); + cpus[i] =3D cpu_devinit(machine->cpu_type, i, hwdef->slavio_base); } =20 /* Create and map RAM frontend */ @@ -855,7 +860,7 @@ static void sun4m_hw_init(MachineState *machine) slavio_intctl =3D slavio_intctl_init(hwdef->intctl_base, hwdef->intctl_base + 0x10000ULL, smp_cpus, - cpu_irqs); + cpus); =20 for (i =3D 0; i < 32; i++) { slavio_irq[i] =3D qdev_get_gpio_in(slavio_intctl, i); --=20 2.43.0 From nobody Mon Apr 13 10:25:04 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 07 Mar 2026 03:29:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Artyom Tarasenko Subject: [PATCH 3/3] hw/timer/slavio_timer: Free resources allocated in instance_init Date: Sat, 7 Mar 2026 11:29:31 +0000 Message-ID: <20260307112931.3322532-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260307112931.3322532-1-peter.maydell@linaro.org> References: <20260307112931.3322532-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772883026290158500 Content-Type: text/plain; charset="utf-8" The slavio_timer device's instance_init function allocates memory for TimerContext structs and a ptimer, but it never frees this memory, so we will leak it if the QMP interface does introspection of this device type, as reported by the clang address sanitizer: Indirect leak of 4896 byte(s) in 17 object(s) allocated from: #0 0x5f2948d9b14d in calloc (/home/pm215/qemu/build/san/qemu-system-spa= rc+0xe0c14d) (BuildId: 7210711bdf6f7fbd0b863bd2dfcc7c42c7175db1) #1 0x758584b11771 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+= 0x63771) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x5f2949097b8a in slavio_timer_init /home/pm215/qemu/build/san/../..= /hw/timer/slavio_timer.c:403:14 #3 0x5f29495d790f in object_initialize_with_type /home/pm215/qemu/build= /san/../../qom/object.c:570:5 #4 0x5f29495d96ef in object_new_with_type /home/pm215/qemu/build/san/..= /../qom/object.c:774:5 #5 0x5f2949a30a26 in qmp_device_list_properties /home/pm215/qemu/build/= san/../../qom/qom-qmp-cmds.c:206:11 Indirect leak of 1632 byte(s) in 17 object(s) allocated from: #0 0x5f2948d9b14d in calloc (/home/pm215/qemu/build/san/qemu-system-spa= rc+0xe0c14d) (BuildId: 7210711bdf6f7fbd0b863bd2dfcc7c42c7175db1) #1 0x758584b11771 in g_malloc0 (/lib/x86_64-linux-gnu/libglib-2.0.so.0+= 0x63771) (BuildId: 116e142b9b52c8a4dfd403e759e71ab8f95d8bb3) #2 0x5f2948f7c65a in ptimer_init /home/pm215/qemu/build/san/../../hw/co= re/ptimer.c:464:9 #3 0x5f2949097c1f in slavio_timer_init /home/pm215/qemu/build/san/../..= /hw/timer/slavio_timer.c:407:32 #4 0x5f29495d790f in object_initialize_with_type /home/pm215/qemu/build= /san/../../qom/object.c:570:5 #5 0x5f29495d96ef in object_new_with_type /home/pm215/qemu/build/san/..= /../qom/object.c:774:5 #6 0x5f2949a30a26 in qmp_device_list_properties /home/pm215/qemu/build/= san/../../qom/qom-qmp-cmds.c:206:11 Avoid the TimerContext leaks by making them an array inside the SLAVIO_TimerState struct instead of allocating a compile-time-fixed number of them each individually with g_new0() and then throwing away the pointer. Avoid the ptimer() leak by calling ptimer_free in instance_finalize(). Signed-off-by: Peter Maydell Reviewed-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/slavio_timer.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 4a3e227fba..eccdc532fb 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -62,20 +62,21 @@ typedef struct CPUTimerState { #define TYPE_SLAVIO_TIMER "slavio_timer" OBJECT_DECLARE_SIMPLE_TYPE(SLAVIO_TIMERState, SLAVIO_TIMER) =20 +typedef struct TimerContext { + MemoryRegion iomem; + SLAVIO_TIMERState *s; + unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU time= rs */ +} TimerContext; + struct SLAVIO_TIMERState { SysBusDevice parent_obj; =20 uint32_t num_cpus; uint32_t cputimer_mode; CPUTimerState cputimer[MAX_CPUS + 1]; + TimerContext timer_context[MAX_CPUS + 1]; }; =20 -typedef struct TimerContext { - MemoryRegion iomem; - SLAVIO_TIMERState *s; - unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU time= rs */ -} TimerContext; - #define SYS_TIMER_SIZE 0x14 #define CPU_TIMER_SIZE 0x10 =20 @@ -400,7 +401,7 @@ static void slavio_timer_init(Object *obj) uint64_t size; char timer_name[20]; =20 - tc =3D g_new0(TimerContext, 1); + tc =3D &s->timer_context[i]; tc->s =3D s; tc->timer_index =3D i; =20 @@ -420,6 +421,15 @@ static void slavio_timer_init(Object *obj) } } =20 +static void slavio_timer_finalize(Object *obj) +{ + SLAVIO_TIMERState *s =3D SLAVIO_TIMER(obj); + + for (int i =3D 0; i <=3D MAX_CPUS; i++) { + ptimer_free(s->cputimer[i].timer); + } +} + static const Property slavio_timer_properties[] =3D { DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), }; @@ -438,6 +448,7 @@ static const TypeInfo slavio_timer_info =3D { .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(SLAVIO_TIMERState), .instance_init =3D slavio_timer_init, + .instance_finalize =3D slavio_timer_finalize, .class_init =3D slavio_timer_class_init, }; =20 --=20 2.43.0