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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772809396; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PGTMgxGA8pFIrhh3yN3K+JOqD7A/a5lQ6jTSkgD0O/c=; b=OJg+Txs8dXFj9dW1Ab9tYvyn4GECTRTMOPaxdRTQGmb78mmK5ySHagY9ellXKCAVuedcxp TDnbd/Q+yl8tWDFmmzzReamZBzwHFVa2P9gYLZMTtOba5asKx/9CqrEelCzXNEjFOlMJBa KXdOIVJRGT0vAcJAsZ+AREe3xeIqMBg= X-MC-Unique: AETrIX8QM_mzgxiMLFU9cw-1 X-Mimecast-MFC-AGG-ID: AETrIX8QM_mzgxiMLFU9cw_1772809392 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v9 1/6] target/arm/cpu: Introduce the infrastructure for cpreg migration tolerances Date: Fri, 6 Mar 2026 16:02:19 +0100 Message-ID: <20260306150302.203112-2-eric.auger@redhat.com> In-Reply-To: <20260306150302.203112-1-eric.auger@redhat.com> References: <20260306150302.203112-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We introduce a datatype for a tolerance with respect to a given cpreg migration issue. The tolerance applies to a given cpreg kvm index, and can be of different types: - ToleranceNotOnBothEnds (cpreg index is allowed to be only present on one end) - ToleranceDiffInMask (value differences are allowed only within a mask) - ToleranceFieldLT (incoming field value must be less than a given value) - ToleranceFieldGT (incoming field value must be greater than a given value) A QLIST of such tolerances can be populated using a new helper: arm_register_cpreg_mig_tolerance() and arm_cpu_match_cpreg_mig_tolerance() allows to check whether a tolerance exists for a given kvm index and its criterion is matched. callers for those helpers will be introduced in subsequent patches. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- v8 -> v9 - fix the tolerance type checking - rename arm_cpu_cpreg_has_mig_tolerance into arm_cpu_match_cpreg_mig_toler= ance --- target/arm/cpu.h | 33 +++++++++++++++++++++ target/arm/cpu.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 108 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 657ff4ab20b..2b1d3af34f0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -843,6 +843,21 @@ struct ARMELChangeHook { QLIST_ENTRY(ARMELChangeHook) node; }; =20 +typedef enum { + ToleranceNotOnBothEnds, + ToleranceDiffInMask, + ToleranceFieldLT, + ToleranceFieldGT, +} ARMCPUCPREGMigToleranceType; + +typedef struct ARMCPUCPREGMigTolerance { + uint64_t kvmidx; + uint64_t mask; + uint64_t value; + ARMCPUCPREGMigToleranceType type; + QLIST_ENTRY(ARMCPUCPREGMigTolerance) node; +} ARMCPUCPREGMigTolerance; + /* These values map onto the return values for * QEMU_PSCI_0_2_FN_AFFINITY_INFO */ typedef enum ARMPSCIState { @@ -1139,6 +1154,7 @@ struct ArchCPU { =20 QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; + QLIST_HEAD(, ARMCPUCPREGMigTolerance) cpreg_mig_tolerances; =20 int32_t node_id; /* NUMA node this CPU belongs to */ =20 @@ -2632,6 +2648,23 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, AR= MELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); =20 +/** + * arm_register_cpreg_mig_tolerance: + * Register a migration tolerance wrt one given cpreg identified by its + * @kvmidx. Only one tolerance can be registered by kvm reg idx. + */ +void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t mask, uint64_t value, + ARMCPUCPREGMigToleranceType type); + +/** + * arm_cpu_match_cpreg_mig_tolerance: + * Check whether a tolerance of type @type exists for a given @kvmidx + * and the tolerance criterion is satified + */ +bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t vmstate_value, uint64_t lo= cal_value, + ARMCPUCPREGMigToleranceType type); /** * arm_rebuild_hflags: * Rebuild the cached TBFLAGS for arbitrary changed processor state. diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7e3e84b4bbb..79e328c2888 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -181,6 +181,75 @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELCha= ngeHookFn *hook, QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node); } =20 +void arm_register_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t mask, uint64_t value, + ARMCPUCPREGMigToleranceType type) +{ + ARMCPUCPREGMigTolerance *t, *entry; + + /* make sure the kvmidx has not tolerance already registered */ + QLIST_FOREACH(t, &cpu->cpreg_mig_tolerances, node) { + if (t->kvmidx =3D=3D kvmidx) { + g_assert_not_reached(); + } + } + entry =3D g_new0(ARMCPUCPREGMigTolerance, 1); + + entry->kvmidx =3D kvmidx; + entry->mask =3D mask; + entry->value =3D value; + entry->type =3D type; + + QLIST_INSERT_HEAD(&cpu->cpreg_mig_tolerances, entry, node); +} + +bool arm_cpu_match_cpreg_mig_tolerance(ARMCPU *cpu, uint64_t kvmidx, + uint64_t vmstate_value, uint64_t lo= cal_value, + ARMCPUCPREGMigToleranceType type) +{ + ARMCPUCPREGMigTolerance *t; + uint64_t diff, diff_outside_mask, field; + bool found =3D false; + + QLIST_FOREACH(t, &cpu->cpreg_mig_tolerances, node) { + if (t->kvmidx =3D=3D kvmidx && t->type =3D=3D type) { + found =3D true; + break; + } + } + if (!found) { + return false; + } + + /* we found one tolerance woth @type associated to the @kvmidx */ + + if (type =3D=3D ToleranceNotOnBothEnds) { + return true; + } + + /* Need to check the mask */ + diff =3D vmstate_value ^ local_value; + diff_outside_mask =3D diff & ~t->mask; + + if (diff_outside_mask) { + /* there are differences outside of the mask */ + return false; + } + if (type =3D=3D ToleranceDiffInMask) { + /* differences only in the field, tolerance matched */ + return true; + } + /* need to compare field value against authorized ones */ + field =3D vmstate_value & t->mask; + if (type =3D=3D ToleranceFieldLT && (field < t->value)) { + return true; + } + if (type =3D=3D ToleranceFieldGT && (field > t->value)) { + return true; + } + return false; +} + static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) { /* Reset a single ARMCPRegInfo register */ @@ -1106,6 +1175,7 @@ static void arm_cpu_initfn(Object *obj) =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); + QLIST_INIT(&cpu->cpreg_mig_tolerances); =20 #ifdef CONFIG_USER_ONLY # ifdef TARGET_AARCH64 @@ -1550,6 +1620,7 @@ static void arm_cpu_finalizefn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMELChangeHook *hook, *next; + ARMCPUCPREGMigTolerance *t, *n; =20 g_hash_table_destroy(cpu->cp_regs); =20 @@ -1561,6 +1632,10 @@ static void arm_cpu_finalizefn(Object *obj) QLIST_REMOVE(hook, node); g_free(hook); } + QLIST_FOREACH_SAFE(t, &cpu->cpreg_mig_tolerances, node, n) { + QLIST_REMOVE(t, node); + g_free(t); + } #ifndef CONFIG_USER_ONLY if (cpu->pmu_timer) { timer_free(cpu->pmu_timer); --=20 2.53.0 From nobody Mon Apr 6 16:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1772809436; cv=none; d=zohomail.com; s=zohoarc; b=fGMqvDJ6XbZ7LNeCJe+S0se4FAcuLCr/ej1GTpqoWJhAZt6jDHOAYkNysvgt7z/fciaMZtoxSam6kRgKhdqcPQUSSGN3Wx2UZkmYgYa51xOFtjI6g+x9xOTKB2z/lxGybX8L1wsLBOlpZJqGgwSmRxcjzmROvYkMJTrKT28xiXQ= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" If there is a mismatch between the cpreg indexes found on both ends, check whether a tolerance was registered for the given kvmidx. If any, silence warning/errors. Create dedicated helper functions that print the name of the culprit reg and analyze whether a tolerance is set. According set the level of traces and analyze whether the migration must eventually fail. Signed-off-by: Eric Auger --- target/arm/machine.c | 21 +++++++++++++++------ target/arm/trace-events | 2 ++ 2 files changed, 17 insertions(+), 6 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 476dad00ee7..fa236431a8b 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -1065,25 +1065,34 @@ static void handle_cpreg_missing_in_incoming_stream= (ARMCPU *cpu, uint64_t kvmidx { g_autofree gchar *name =3D print_register_name(kvmidx); =20 + if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, + 0, 0, ToleranceNotOnBothEnds)) { + trace_tolerate_cpreg_missing_in_incoming_stream(name); + return; + } warn_report("%s: %s " "expected by the destination but not in the incoming strea= m: " "skip it", __func__, name); } =20 /* - * Handle the situation where @kvmidx is in the incoming stream - * but not on destination. This currently fails the migration but - * we plan to accomodate some exceptions, hence the boolean returned value. + * Handle the situation where @kvmidx is in the incoming + * stream but not on destination. This fails the migration if + * no cpreg mig tolerance is matched for this @kvmidx + * Return true if the migration shall eventually fail */ static bool handle_cpreg_only_in_incoming_stream(ARMCPU *cpu, uint64_t kvm= idx) { g_autofree gchar *name =3D print_register_name(kvmidx); - bool fail =3D true; =20 + if (arm_cpu_match_cpreg_mig_tolerance(cpu, kvmidx, + 0, 0, ToleranceNotOnBothEnds)) { + trace_tolerate_cpreg_only_in_incoming_stream(name); + return false; + } error_report("%s: %s in the incoming stream but unknown on the " "destination: fail migration", __func__, name); - - return fail; + return true; } =20 static int cpu_post_load(void *opaque, int version_id) diff --git a/target/arm/trace-events b/target/arm/trace-events index 2de0406f784..8502fb3265c 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -29,3 +29,5 @@ arm_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint= 64_t x3, uint32_t cpuid =20 # machine.c cpu_post_load(uint32_t cpreg_vmstate_array_len, uint32_t cpreg_array_len) = "cpreg_vmstate_array_len=3D%d cpreg_array_len=3D%d" +tolerate_cpreg_missing_in_incoming_stream(char *name) "%s is missing in in= coming stream but this is explicitly tolerated" +tolerate_cpreg_only_in_incoming_stream(char *name) "%s is in incoming stre= am but not on destination but this is explicitly tolerated" --=20 2.53.0 From nobody Mon Apr 6 16:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772809404; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=eldssNcwL2vzqR/skuruxhEOMx/slaPtYj/2cYe4PG0=; b=JE4mOVYsZFrNuMq0geAzbZtNhrWDoXXYYx7CmWJ5B7HUt2e2VV0VlubDFefwyOTNX08xIx x8jFB8JXAwtYGReIbxVQRysUoY8m9PriC0fYiyxvn3yCx587A7nLb+mWYOi5r6yqf7ISyi rtMvAxNCr8B436hTjDJwaqcnOKhShRc= X-MC-Unique: gspfo7W7O96rgc5S92frEw-1 X-Mimecast-MFC-AGG-ID: gspfo7W7O96rgc5S92frEw_1772809400 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v9 3/6] target/arm/cpu64: Mitigate migration failures due to spurious TCR_EL1, PIRE0_EL1 and PIR_EL1 Date: Fri, 6 Mar 2026 16:02:21 +0100 Message-ID: <20260306150302.203112-4-eric.auger@redhat.com> In-Reply-To: <20260306150302.203112-1-eric.auger@redhat.com> References: <20260306150302.203112-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -9 X-Spam_score: -1.0 X-Spam_bar: - X-Spam_report: (-1.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.411, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.679, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1772809659543158500 Before linux v6.13 those registers were erroneously unconditionally exposed and this was fixed by commits: - 0fcb4eea5345 ("KVM: arm64: Hide TCR2_EL1 from userspace when disabled for guests") - a68cddbe47ef=C2=A0("KVM: arm64: Hide S1PIE registers from userspace when disabled for guests") in v6.13. This means if we migrate from an old kernel host to a >=3D 6.13 kernel host, migration currently fails. Declare cpreg migration tolerance for those registers. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/cpu64.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d6feba220e8..4cfddc6e8c0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -810,6 +810,31 @@ static void aarch64_a53_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *cpu) +{ + /* + * Registers that may be in the incoming stream and not exposed + * on the destination + */ + + /* + * TCR_EL1 was erroneously unconditionnally exposed before linux v6.13. + * See commit 0fcb4eea5345 ("KVM: arm64: Hide TCR2_EL1 from userspace + * when disabled for guests") + */ + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 2, 0, 3), + 0, 0, ToleranceNotOnBothEnds); + /* + * PIRE0_EL1 and PIR_EL1 were erroneously unconditionnally exposed + * before linux v6.13. See commit a68cddbe47ef=C2=A0("KVM: arm64: Hide + * S1PIE registers from userspace when disabled for guests") + */ + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 2), + 0, 0, ToleranceNotOnBothEnds); + arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3), + 0, 0, ToleranceNotOnBothEnds); +} + static void aarch64_host_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -822,6 +847,7 @@ static void aarch64_host_initfn(Object *obj) #endif =20 #if defined(CONFIG_KVM) + kvm_arm_set_cpreg_mig_tolerances(cpu); kvm_arm_set_cpu_features_from_host(cpu); aarch64_add_sve_properties(obj); #elif defined(CONFIG_HVF) --=20 2.53.0 From nobody Mon Apr 6 16:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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b=cbK3NUMtW5S9h+pFQB/3kP9icI/sw8M4ZmE++fLkoMzk0+zItRnTaDPY+zDvl/Z5CH37lt 1lyIJAyo0oRm4P92uNWoFuVt0ckPPJewHWvkLn397glgFby0UX36aQXD9c7ElH8pbk1Jkq /wggQD148hJt6SVeP2956pR5DcjW1+o= X-MC-Unique: 2yXIGyvuOM2EG4vEfwBQIA-1 X-Mimecast-MFC-AGG-ID: 2yXIGyvuOM2EG4vEfwBQIA_1772809403 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v9 4/6] target/arm/cpu64: Define cpreg migration tolerance for KVM_REG_ARM_VENDOR_HYP_BMAP_2 Date: Fri, 6 Mar 2026 16:02:22 +0100 Message-ID: <20260306150302.203112-5-eric.auger@redhat.com> In-Reply-To: <20260306150302.203112-1-eric.auger@redhat.com> References: <20260306150302.203112-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register is exposed from v6.15 onwards. Backward migration from a >=3D v6.15 to an older kernel would fail without cpreg migration tolerance definition for this register. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4cfddc6e8c0..abc6b78ef7d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -833,6 +833,14 @@ static void kvm_arm_set_cpreg_mig_tolerances(ARMCPU *c= pu) 0, 0, ToleranceNotOnBothEnds); arm_register_cpreg_mig_tolerance(cpu, ARM64_SYS_REG(3, 0, 10, 2, 3), 0, 0, ToleranceNotOnBothEnds); + + /* + * KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register is exposed + * from v6.15 onwards. Backward migration from a >=3D v6.15 to an older + * kernel would fail without cpreg migration tolerance definition + */ + arm_register_cpreg_mig_tolerance(cpu, KVM_REG_ARM_FW_FEAT_BMAP_REG(3), + 0, 0, ToleranceNotOnBothEnds); } =20 static void aarch64_host_initfn(Object *obj) --=20 2.53.0 From nobody Mon Apr 6 16:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1772809754; cv=none; d=zohomail.com; s=zohoarc; b=fcJzNj6VHI800mGUprJ0ilEAuOfL0C4GmLMxLX0Wy7Ak3DQLnw+UnD511japM8L1NmUgO/nHpfHLhLhq1vl8bNVUdwO4CpyYkvPbJfLGsOi3aktn1+OEl/awWhXYUXXcmpMLF3QlbHk0pV1Qx/A36lIhOzYMNRcFIdnAEOqEqiA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772809754; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Fri, 6 Mar 2026 15:03:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772809411; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TFsl187R44lG9HulMdktrp/axdkCWvzZ/ZzMM/y1sLQ=; b=Y4lpjnWMVMANNDa2GfcELrNf6XDfn12VcPYds9XeUDVyP8Ua7CnBlw4J3BfKGXACGaHDGV gX0tSpGZm5S/eN6SOPnwYyTUICqwcIQGgoxUlDxdB7Nw8d94rHi/QeB59jaPgkOT7Qik5q RmqmNjRycJzU4eMVhha0ZG+Rb5M1Py8= X-MC-Unique: _xMrjcWiMWiXJSkPFZ2Mcg-1 X-Mimecast-MFC-AGG-ID: _xMrjcWiMWiXJSkPFZ2Mcg_1772809407 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v9 5/6] target/arm/helper: Define cpreg migration tolerance for DGBDTR_EL0 Date: Fri, 6 Mar 2026 16:02:23 +0100 Message-ID: <20260306150302.203112-6-eric.auger@redhat.com> In-Reply-To: <20260306150302.203112-1-eric.auger@redhat.com> References: <20260306150302.203112-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" We want to remove AArch32 DBGDTRTX which was erroneously exposed. This was attempted by 655659a74a36b ("target/arm: Correct encoding of Debug Communications Channel registers") but it was discovered that the removal of this debug register broke forward migration on TCG. Now we have the cpreg migration tolerance infrastructure, we can declare one for the DBGDTRTX. This allow to revert the reinstate patch. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7389f2988c4..3cba62705dc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6426,9 +6426,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fgt =3D FGT_CLIDR_EL1, .resetvalue =3D GET_IDREG(isar, CLIDR) }; + uint64_t dbgtr_el0_kvmidx =3D + cpreg_to_kvm_id(ENCODE_CP_REG(14, 0, 1, 0, 5, 3, 0)); + define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + arm_register_cpreg_mig_tolerance(cpu, dbgtr_el0_kvmidx, + 0, 0, ToleranceNotOnBothEnds); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } --=20 2.53.0 From nobody Mon Apr 6 16:12:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=XrK5sjsyGep9Yp+CQgZDC912w7MjYPv/eTMvkckolrgbvzkOA+zz76HhsMT3fqW8eiqEam fmLgP8IoOjiuJQmyPquosnuZ0PLMTTp8BmG1/qYzSKEbHYwTgms3MF9d6yptGuXELFYL/t yCqPiL5ubBFH/IsSa2SE8YlLI4EoJ7o= X-MC-Unique: ze1-QmW3M56xi3J83QUZMA-1 X-Mimecast-MFC-AGG-ID: ze1-QmW3M56xi3J83QUZMA_1772809411 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, sebott@redhat.com, peterx@redhat.com, philmd@linaro.org, alex.bennee@linaro.org Subject: [PATCH v9 6/6] Revert "target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat" Date: Fri, 6 Mar 2026 16:02:24 +0100 Message-ID: <20260306150302.203112-7-eric.auger@redhat.com> In-Reply-To: <20260306150302.203112-1-eric.auger@redhat.com> References: <20260306150302.203112-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This reverts commit 4f2b82f60431 ("target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat). We don't need that commit anymore as the AArch32 DBGDTRTX register is declared to be safe to ignore in the incoming migration stream. Signed-off-by: Eric Auger Reviewed-by: Sebastian Ott --- target/arm/debug_helper.c | 29 ----------------------------- 1 file changed, 29 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 352c8e5c8e7..8477ca5def6 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -171,13 +171,6 @@ static void dbgclaimclr_write(CPUARMState *env, const = ARMCPRegInfo *ri, env->cp15.dbgclaim &=3D ~(value & 0xFF); } =20 -static CPAccessResult access_bogus(CPUARMState *env, const ARMCPRegInfo *r= i, - bool isread) -{ - /* Always UNDEF, as if this cpreg didn't exist */ - return CP_ACCESS_UNDEFINED; -} - static const ARMCPRegInfo debug_cp_reginfo[] =3D { /* * DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped @@ -240,28 +233,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .opc0 =3D 2, .opc1 =3D 3, .crn =3D 0, .crm =3D 4, .opc2 =3D 0, .access =3D PL0_RW, .accessfn =3D access_tdcc, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - /* - * This is not a real AArch32 register. We used to incorrectly expose - * this due to a QEMU bug; to avoid breaking migration compatibility we - * need to continue to provide it so that we don't fail the inbound - * migration when it tells us about a sysreg that we don't have. - * We set an always-fails .accessfn, which means that the guest doesn't - * actually see this register (it will always UNDEF, identically to if - * there were no cpreg definition for it other than that we won't print - * a LOG_UNIMP message about it), and we set the ARM_CP_NO_GDB flag so= the - * gdbstub won't see it either. - * (We can't just set .access =3D 0, because add_cpreg_to_hashtable() - * helpfully ignores cpregs which aren't accessible to the highest - * implemented EL.) - * - * TODO: implement a system for being able to describe "this register - * can be ignored if it appears in the inbound stream"; then we can - * remove this temporary hack. - */ - { .name =3D "BOGUS_DBGDTR_EL0", .state =3D ARM_CP_STATE_AA32, - .cp =3D 14, .opc1 =3D 3, .crn =3D 0, .crm =3D 5, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D access_bogus, - .type =3D ARM_CP_CONST | ARM_CP_NO_GDB, .resetvalue =3D 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system * to access the contents of EDECCR. EDECCR is not implemented though, --=20 2.53.0