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[81.2.115.145]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-485246ece8bsm28681845e9.4.2026.03.06.07.00.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 07:00:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1772809232; x=1773414032; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=lPAVCki5fzTClwwWXBog13/g0q9UBCatamyseofWAHE=; b=AEW5ouEKgIrAHpMMIM7pVNQiunVxo/tBxpseeNkkZihXmvcOnhQ3rVPUHmAgGD/p/2 QMGcyUHc2EFh6H2FRiIYgHnrbzDz974U1mDu7nHCUJvQut6RdfTmrw036xtsWEkoheb2 elt00DPaP8YNSjwZo54dzJi0XSzeq7C2MAZDUb8mxkBxamAVJU1yuWLED6QdcjUsvPHd Y7Rkf9PUq4MUL46453zg2RZJJ1AzIz1geh3P4wT4SpXBOzxRe9xPr3hy0Qz1lQDStcu4 B/D+A7S9zWUijGmkPI8BwII9ms/l/92t23oItBIP2C/FGWEU0QHUdHDxfTAwEOn/tyWs Tsew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772809232; x=1773414032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=lPAVCki5fzTClwwWXBog13/g0q9UBCatamyseofWAHE=; b=dw5DFyQS92YA/77tfn0FNagTlX9rls+Cgqk5BEUcPAFkPP4iZYGGNqDl09KmUzeyQF VE/hNAChwWRzh3ITlgQF9vm36PpaSmFCuxtSinfZ6F4le0c4Mo89miqXGQBKd7VvBDEP 6ZXpH6KN7FBgVboxJ/D3YStzlAwij1o8eI+f75Iee2AESD2Kea5UwzFkJ1kfFI0ouOIL 9DbkcCjIw0AKmWRQg/cM0FdFCvYDTiRBaWlgI73IMMKpoajh2aABOOFhRwI2HooxdGtC BbfZtcV8jAU8reBBKYGRZINLuT+p2q7OraaZwe3gvJjXp8kW5Ywlg/tuylGQKNuixi71 ZNpQ== X-Gm-Message-State: AOJu0Yz/R6RgJnf+jKiwjtpE0wy0yQnAHcMnIccE7wqp7gqL991g1Pb9 eS45TxfpiPGph4KVIBlbgekTtwrCGY3+O6y+t89No3lOs7iieRQQfg1d3dLFE2idlJxBhKpY4Pz Z/E2m X-Gm-Gg: ATEYQzzBp3R3/1n8Q5md0daZJVe1qVX/uTFQaCj/AfVjtIXvHUZyE1rmlzuYRoaIT4D IR8Kc8lfk7zRNMDLHGgH4i3mh97VNZeGD5egCOnwiqrPDpyFAeAA84rvh0d1p3h6IvkY/THA+ah Jm2GVSd6YSJxv5+O1R+d2HEFtJS9PwSnCuDZ/UEiq5Qvvkp+EJpa8UIE3r2m70nbHQDKW/5Gyog SyY/ag7P8o3oWFlfog90XnboT702uKr3SLITFwrBKt94yHodYEJjEQjTWVR4GJZwbFik5y9ybSu I73fvof8BEx4Jjg2y8bkOjDGTUqLsGJMBQ1Dt94bDzDuwU9FsrMFBsKFASrev8E20h0U5Bh2G9/ +yji+EvrgVdJn/JiGnrDBrAqxVRF2nP6nXUUdPhzSs/uWzZxt5imfmsH9DCyAeavtRc8E6NH6Kn AyHCfMmIEpaqMaffIWg0tgA7MdXVtofo4JNiTKh4kPPZ3Ax+b8W3sTC5i7Rx2Zm4pNceXUUYrGt xEhOxgVBcu19ryxBVX80GEdHNgauq4= X-Received: by 2002:a05:600c:4591:b0:483:6d4a:7e6d with SMTP id 5b1f17b1804b1-48526978644mr35776515e9.30.1772809231415; Fri, 06 Mar 2026 07:00:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/49] hvf: gate ARM_FEATURE_PMU register emulation behind not being at EL2 Date: Fri, 6 Mar 2026 14:59:33 +0000 Message-ID: <20260306145939.2162189-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306145939.2162189-1-peter.maydell@linaro.org> References: <20260306145939.2162189-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1772809407919158500 From: Mohamed Mediouni From Apple documentation: > When EL2 is disabled, PMU register accesses trigger "Trapped MSR, MRS, or > System Instruction" exceptions. When this happens, hv_vcpu_run()=E2=80=AF= returns, and the > =E2=80=AFhv_vcpu_exit_t=E2=80=AFobject contains the information about thi= s exception. > When EL2 is enabled, the handling of PMU register accesses is determined = by the PMUVer > field of ID_AA64DFR0_EL1=E2=80=AFregister. > If the PMUVer=E2=80=AFfield value is zero or is invalid, PMU register acc= esses generate "Undefined" > exceptions, which are sent to the guest. > If the PMUVer=E2=80=AFfield value is non-zero and valid, PMU register acc= esses are emulated by the framework. > The ID_AA64DFR0_EL1=E2=80=AFregister can be modified via hv_vcpu_set_sys_= reg=E2=80=AFAPI. Signed-off-by: Mohamed Mediouni Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20260306130107.35359-12-mohamed@unpredictable.fr Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8363e10eff..91bbb2013b 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1589,7 +1589,7 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t re= g, uint64_t *val) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; =20 - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_nested_virt_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCR_EL0: *val =3D env->cp15.c9_pmcr; @@ -1850,7 +1850,7 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t r= eg, uint64_t val) SYSREG_OP2(reg), val); =20 - if (arm_feature(env, ARM_FEATURE_PMU)) { + if (!hvf_nested_virt_enabled() && arm_feature(env, ARM_FEATURE_PMU)) { switch (reg) { case SYSREG_PMCCNTR_EL0: pmu_op_start(env); --=20 2.43.0