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Signed-off-by: Manos Pitsidianakis Reviewed-by: Mohamed Mediouni Message-id: 20260306-sme2-hvf-v7-2-e72eeda41ed3@linaro.org Signed-off-by: Peter Maydell --- target/arm/hvf/hvf.c | 36 +++++++++++++++++++++++------------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 21b16dfe42..5fc8f6bbbd 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -315,6 +315,7 @@ typedef struct ARMHostCPUFeatures { uint64_t features; uint64_t midr; uint32_t reset_sctlr; + uint32_t sme_vq_supported; const char *dtb_compatible; } ARMHostCPUFeatures; =20 @@ -1106,6 +1107,24 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPU= Features *ahcf) r |=3D hv_vcpu_config_get_feature_reg(config, regs[i].reg, &host_isar.idregs[regs[i].inde= x]); } + + if (__builtin_available(macOS 15.2, *)) { + static const struct sme_isar_regs { + hv_feature_reg_t reg; + ARMIDRegisterIdx index; + } sme_regs[] =3D { + { HV_FEATURE_REG_ID_AA64SMFR0_EL1, ID_AA64SMFR0_EL1_IDX }, + { HV_FEATURE_REG_ID_AA64ZFR0_EL1, ID_AA64ZFR0_EL1_IDX }, + }; + + if (hvf_arm_sme2_supported()) { + for (i =3D 0; i < ARRAY_SIZE(sme_regs); i++) { + r |=3D hv_vcpu_config_get_feature_reg(config, sme_regs[i].= reg, + &host_isar.idregs[sme_= regs[i].index]); + } + } + } + os_release(config); =20 /* @@ -1121,19 +1140,6 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPU= Features *ahcf) =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 - /* - * Disable SME, which is not properly handled by QEMU hvf yet. - * To allow this through we would need to: - * - make sure that the SME state is correctly handled in the - * get_registers/put_registers functions - * - get the SME-specific CPU properties to work with accelerators - * other than TCG - * - fix any assumptions we made that SME implies SVE (since - * on the M4 there is SME but not SVE) - */ - SET_IDREG(&host_isar, ID_AA64PFR1, - GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); - ahcf->isar =3D host_isar; =20 /* @@ -1148,6 +1154,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) */ ahcf->reset_sctlr |=3D 0x00800000; =20 + ahcf->sme_vq_supported =3D hvf_arm_sme2_supported() ? hvf_arm_sme2_get= _svl() : 0; + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) !=3D 0x11) { return false; @@ -1199,6 +1207,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->env.features =3D arm_host_cpu_features.features; cpu->midr =3D arm_host_cpu_features.midr; cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; + cpu->sme_vq.supported =3D arm_host_cpu_features.sme_vq_supported; } =20 void hvf_arch_vcpu_destroy(CPUState *cpu) @@ -1343,6 +1352,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 + aarch64_add_sme_properties(OBJECT(cpu)); return 0; } =20 --=20 2.43.0