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charset="utf-8" This patch adds new model for Axiado SoC AX3000 which supports 4 Cortex-A53 ARM64 CPUs Arm Generic Interrupt Controller v3 4 Cadence UARTs 1 SDHCI controller with PHY Signed-off-by: Kuan-Jui Chiu --- hw/arm/Kconfig | 8 + hw/arm/axiado-soc.c | 287 ++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 2 + include/hw/arm/axiado-soc.h | 152 +++++++++++++++++++ 4 files changed, 449 insertions(+) create mode 100644 hw/arm/axiado-soc.c create mode 100644 include/hw/arm/axiado-soc.h diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index c66c452737..a91b81b298 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -699,3 +699,11 @@ config ARMSSE select UNIMP select SSE_COUNTER select SSE_TIMER + +config AXIADO_SOC + bool + default y + depends on ARM + select ARM_GIC + select CADENCE # UART + select SDHCI diff --git a/hw/arm/axiado-soc.c b/hw/arm/axiado-soc.c new file mode 100644 index 0000000000..e23410c147 --- /dev/null +++ b/hw/arm/axiado-soc.c @@ -0,0 +1,287 @@ +/* + * Axiado SoC AX3000 + * + * Author: Kuan-Jui Chiu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "system/address-spaces.h" +#include "hw/arm/bsa.h" +#include "hw/arm/axiado-soc.h" +#include "system/system.h" +#include "qobject/qlist.h" +#include "qom/object.h" + +static uint64_t sdhci_phy_read(void *opaque, hwaddr offset, unsigned size) +{ + uint32_t val =3D 0x00; + + switch (offset) { + case REG_ID: + val =3D 0x3dff6870; + break; + case REG_STATUS: + // Make DLL_RDY | CAL_DONE + val =3D (1u << 0) | (1u << 6); + break; + default: + break; + } + + return val; +} + +static void sdhci_phy_write(void *opaque, hwaddr offset, uint64_t val, uns= igned size) +{ + /* TBD */ +} + +static const MemoryRegionOps sdhci_phy_ops =3D { + .read =3D sdhci_phy_read, + .write =3D sdhci_phy_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t timer_ctrl_read(void *opaque, hwaddr offset, unsigned size) +{ + return 0x0; +} + +static void timer_ctrl_write(void *opaque, hwaddr offset, uint64_t val, un= signed size) +{ + /* TBD */ +} + +static const MemoryRegionOps timer_ctrl_ops =3D { + .read =3D timer_ctrl_read, + .write =3D timer_ctrl_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size) +{ + switch (offset) { + case CLKRST_CPU_PLL_POSTDIV_OFFSET: + return 0x20891b; + case CLKRST_CPU_PLL_STS_OFFSET: + return 0x01; + default: + return 0x00; + } +} + +static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned = size) +{ + /* TBD */ +} + +static const MemoryRegionOps pll_ops =3D { + .read =3D pll_read, + .write =3D pll_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void ax3000_init(Object *obj) +{ + AxiadoSoCState *s =3D AXIADO_SOC(obj); + AxiadoSoCClass *sc =3D AXIADO_SOC_GET_CLASS(s); + int i; + + for (i =3D 0; i < sc->num_cpus; i++) { + g_autofree char *name =3D g_strdup_printf("cpu%d", i); + object_initialize_child(obj, name, &s->cpu[i], ARM_CPU_TYPE_NAME("= cortex-a53")); + } + + object_initialize_child(obj, "gic", &s->gic, gicv3_class_name()); + + for (i =3D 0; i < AX3000_NUM_UARTS; i++) { + g_autofree char *name =3D g_strdup_printf("uart%d", i); + object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART); + } + + object_initialize_child(obj, "sdhci0", &s->sdhci0, TYPE_SYSBUS_SDHCI); +} + +static void ax3000_realize(DeviceState *dev, Error **errp) +{ + AxiadoSoCState *s =3D AXIADO_SOC(dev); + AxiadoSoCClass *sc =3D AXIADO_SOC_GET_CLASS(s); + SysBusDevice *gicsbd =3D SYS_BUS_DEVICE(&s->gic); + DeviceState *gicdev =3D DEVICE(&s->gic); + QList *redist_region_count; + int i; + + /* CPUs */ + for (i =3D 0; i < sc->num_cpus; i++) { + object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 8000000, + &error_abort); + + if (object_property_find(OBJECT(&s->cpu[i]), "has_el3")) { + object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", + false, &error_abort); + } + + if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) { + return; + } + } + + /* GIC */ + qdev_prop_set_uint32(gicdev, "num-cpu", sc->num_cpus); + qdev_prop_set_uint32(gicdev, "num-irq", + AX3000_NUM_IRQS + GIC_INTERNAL); + + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, sc->num_cpus); + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count= ); + + if (!sysbus_realize(gicsbd, errp)) { + return; + } + + sysbus_mmio_map(gicsbd, 0, AX3000_GIC_DIST_BASE); + sysbus_mmio_map(gicsbd, 1, AX3000_GIC_REDIST_BASE); + + /* + * Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, and + * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs. + */ + for (i =3D 0; i < sc->num_cpus; i++) { + DeviceState *cpudev =3D DEVICE(&s->cpu[i]); + int intidbase =3D AX3000_NUM_IRQS + i * GIC_INTERNAL; + qemu_irq irq; + + /* + * Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs. + */ + static const int timer_irqs[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ + }; + + for (int j =3D 0; j < ARRAY_SIZE(timer_irqs); j++) { + irq =3D qdev_get_gpio_in(gicdev, intidbase + timer_irqs[j]); + qdev_connect_gpio_out(cpudev, j, irq); + } + + irq =3D qdev_get_gpio_in(gicdev, intidbase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", + 0, irq); + + sysbus_connect_irq(gicsbd, i, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(gicsbd, i + sc->num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicsbd, i + 2 * sc->num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicsbd, i + 3 * sc->num_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } + + /* DRAM */ + for (i =3D 0; i < AX3000_NUM_BANKS; i++) { + struct { + hwaddr addr; + size_t size; + const char *name; + } dram_table[] =3D { + { AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, "dram0" }, + { AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, "dram1" } + }; + + memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name, + dram_table[i].size, &error_fatal); + memory_region_add_subregion(get_system_memory(), dram_table[i].add= r, + &s->dram[i]); + } + + /* UARTs */ + for (i =3D 0; i < AX3000_NUM_UARTS; i++) { + struct { + hwaddr addr; + unsigned int irq; + } serial_table[] =3D { + { AX3000_UART0_BASE, AX3000_UART0_IRQ }, + { AX3000_UART1_BASE, AX3000_UART1_IRQ }, + { AX3000_UART2_BASE, AX3000_UART2_IRQ }, + { AX3000_UART3_BASE, AX3000_UART3_IRQ } + }; + + qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i)); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].ad= dr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, + qdev_get_gpio_in(gicdev, serial_table[i].irq)); + } + + /* Timer control*/ + memory_region_init_io(&s->timer_ctrl, OBJECT(s), &timer_ctrl_ops, s, + "timer_ctrl", 32); + memory_region_add_subregion(get_system_memory(), AX3000_TIMER_CTRL, + &s->timer_ctrl); + + /* PLL control */ + memory_region_init_io(&s->pll_ctrl, OBJECT(s), &pll_ops, s, "pll_ctrl", + 32); + memory_region_add_subregion(get_system_memory(), AX3000_PLL_BASE, + &s->pll_ctrl); + + /* SDHCI */ + qdev_prop_set_uint64(DEVICE(&s->sdhci0), "capareg", 0x216737eed0b0); + qdev_prop_set_uint64(DEVICE(&s->sdhci0), "sd-spec-version", 3); + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci0), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci0), 0, AX3000_SDHCI0_BASE); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci0), 0, + qdev_get_gpio_in(gicdev, AX3000_SDHCI0_IRQ)); + + memory_region_init_io(&s->sdhci_phy, OBJECT(s), &sdhci_phy_ops, s, + "sdhci_phy", AX3000_SDHCI0_PHY_SIZE); + memory_region_add_subregion(get_system_memory(), AX3000_SDHCI0_PHY_BAS= E, + &s->sdhci_phy); +} + +static void ax3000_class_init(ObjectClass *oc, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + AxiadoSoCClass *sc =3D AXIADO_SOC_CLASS(oc); + + dc->desc =3D "Axiado SoC AX3000"; + dc->realize =3D ax3000_realize; + sc->num_cpus =3D AX3000_NUM_CPUS; +} + +static const TypeInfo axiado_soc_types[] =3D { + { + .name =3D TYPE_AXIADO_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(AxiadoSoCState), + .instance_init =3D ax3000_init, + .class_init =3D ax3000_class_init, + } +}; + +DEFINE_TYPES(axiado_soc_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 47cdc51d13..c3c96c0a70 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -105,6 +105,8 @@ arm_common_ss.add(when: 'CONFIG_STRONGARM', if_true: fi= les('strongarm.c')) arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'= )) arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c')) +arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: = files( + 'axiado-soc.c')) =20 arm_common_ss.add(files('boot.c')) =20 diff --git a/include/hw/arm/axiado-soc.h b/include/hw/arm/axiado-soc.h new file mode 100644 index 0000000000..2483bdd8c2 --- /dev/null +++ b/include/hw/arm/axiado-soc.h @@ -0,0 +1,152 @@ +/* + * Axiado SoC AX3000 + * + * Author: Kuan-Jui Chiu + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef AXIADO_AX3000_H +#define AXIADO_AX3000_H + +#include "cpu.h" +#include "hw/intc/arm_gicv3_common.h" +#include "hw/char/cadence_uart.h" +#include "hw/sd/sdhci.h" +#include "hw/core/sysbus.h" +#include "qemu/units.h" + +#define TYPE_AXIADO_SOC "ax3000" +OBJECT_DECLARE_TYPE(AxiadoSoCState, AxiadoSoCClass, AXIADO_SOC) + +#define AX3000_RAM_START 0x3C000000 +#define AX3000_RAM_SIZE_MAX (16 * GiB) + +#define AX3000_DRAM0_BASE AX3000_RAM_START +#define AX3000_DRAM0_SIZE (1088 * MiB) +#define AX3000_DRAM1_BASE 0x400000000 +#define AX3000_DRAM1_SIZE (2 * GiB) + +#define AX3000_GIC_DIST_BASE 0x80300000 +#define AX3000_GIC_DIST_SIZE (64 * KiB) +#define AX3000_GIC_REDIST_BASE 0x80380000 +#define AX3000_GIC_REDIST_SIZE (512 * KiB) + +#define AX3000_UART0_BASE 0x80520000 +#define AX3000_UART0_SIZE (256) +#define AX3000_UART1_BASE 0x805a0000 +#define AX3000_UART1_SIZE (256) +#define AX3000_UART2_BASE 0x80620000 +#define AX3000_UART2_SIZE (256) +#define AX3000_UART3_BASE 0x80520800 +#define AX3000_UART3_SIZE (256) + +#define AX3000_SDHCI0_BASE 0x86000000 +#define AX3000_SDHCI0_PHY_BASE 0x80801C00 +#define AX3000_SDHCI0_PHY_SIZE (256) + +#define AX3000_GPIO0_BASE 0x80500000 +#define AX3000_GPIO0_SIZE (1024) +#define AX3000_GPIO1_BASE 0x80580000 +#define AX3000_GPIO1_SIZE (1024) +#define AX3000_GPIO2_BASE 0x80600000 +#define AX3000_GPIO2_SIZE (1024) +#define AX3000_GPIO3_BASE 0x80680000 +#define AX3000_GPIO3_SIZE (1024) +#define AX3000_GPIO4_BASE 0x80700000 +#define AX3000_GPIO4_SIZE (1024) +#define AX3000_GPIO5_BASE 0x80780000 +#define AX3000_GPIO5_SIZE (1024) +#define AX3000_GPIO6_BASE 0x80800000 +#define AX3000_GPIO6_SIZE (1024) +#define AX3000_GPIO7_BASE 0x80880000 +#define AX3000_GPIO7_SIZE (1024) + +#define AX3000_TIMER_CTRL 0x8A020000 +#define AX3000_PLL_BASE 0x80000000 +#define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C +#define CLKRST_CPU_PLL_STS_OFFSET 0x14 + + +enum Ax3000Configuration { + AX3000_NUM_CPUS =3D 4, + AX3000_NUM_IRQS =3D 224, + AX3000_NUM_BANKS =3D 2, + AX3000_NUM_UARTS =3D 4, + AX3000_NUM_GPIOS =3D 8, +}; + +typedef struct AxiadoSoCState { + SysBusDevice parent; + + ARMCPU cpu[AX3000_NUM_CPUS]; + GICv3State gic; + MemoryRegion dram[AX3000_NUM_BANKS]; + MemoryRegion timer_ctrl; + MemoryRegion pll_ctrl; + CadenceUARTState uart[AX3000_NUM_UARTS]; + SDHCIState sdhci0; + MemoryRegion sdhci_phy; +} AxiadoSoCState; + +typedef struct AxiadoSoCClass { + SysBusDeviceClass parent; + + uint32_t num_cpus; +} AxiadoSoCClass; + +enum Ax3000MemoryRegions { + AX3000_GIC_DIST, + AX3000_GIC_REDIST, + AX3000_DRAM0, + AX3000_DRAM1, + AX3000_UART0, + AX3000_UART1, + AX3000_UART2, + AX3000_UART3, + AX3000_SDHCI0, + AX3000_GPIO0, + AX3000_GPIO1, + AX3000_GPIO2, + AX3000_GPIO3, + AX3000_GPIO4, + AX3000_GPIO5, + AX3000_GPIO6, + AX3000_GPIO7, +}; + +enum Ax3000Irqs { + AX3000_UART0_IRQ =3D 112, + AX3000_UART1_IRQ =3D 113, + AX3000_UART2_IRQ =3D 114, + AX3000_UART3_IRQ =3D 170, + + AX3000_SDHCI0_IRQ =3D 123, + + AX3000_GPIO0_IRQ =3D 183, + AX3000_GPIO1_IRQ =3D 184, + AX3000_GPIO2_IRQ =3D 185, + AX3000_GPIO3_IRQ =3D 186, + AX3000_GPIO4_IRQ =3D 187, + AX3000_GPIO5_IRQ =3D 188, + AX3000_GPIO6_IRQ =3D 189, + AX3000_GPIO7_IRQ =3D 190, +}; + +enum SDHCI_PHY_REG { + REG_ID =3D 0x00, // ID + REG_STATUS =3D 0x50, // READY/LOCK/CAL_DONE bits +}; + +#endif /* AXIADO_AX3000_H */ --=20 2.34.1