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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=57.103.68.16; envelope-from=mohamed@unpredictable.fr; helo=outbound.mr.icloud.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @unpredictable.fr) X-ZM-MESSAGEID: 1772784197786158500 Content-Type: text/plain; charset="utf-8" From: Manos Pitsidianakis Starting from M4 cores and MacOS 15.2 SDK, HVF can virtualise FEAT_SME2. Signed-off-by: Manos Pitsidianakis Reviewed-by: Richard Henderson Message-Id: <20260303-sme2-hvf-v6-2-b473702d8287@linaro.org> --- target/arm/hvf/hvf.c | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 3d194680cc..c9787b3ea1 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -315,6 +315,7 @@ typedef struct ARMHostCPUFeatures { uint64_t features; uint64_t midr; uint32_t reset_sctlr; + uint32_t sme_vq_supported; const char *dtb_compatible; } ARMHostCPUFeatures; =20 @@ -1121,19 +1122,6 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPU= Features *ahcf) =20 clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar); =20 - /* - * Disable SME, which is not properly handled by QEMU hvf yet. - * To allow this through we would need to: - * - make sure that the SME state is correctly handled in the - * get_registers/put_registers functions - * - get the SME-specific CPU properties to work with accelerators - * other than TCG - * - fix any assumptions we made that SME implies SVE (since - * on the M4 there is SME but not SVE) - */ - SET_IDREG(&host_isar, ID_AA64PFR1, - GET_IDREG(&host_isar, ID_AA64PFR1) & ~R_ID_AA64PFR1_SME_MASK= ); - ahcf->isar =3D host_isar; =20 /* @@ -1148,6 +1136,8 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUF= eatures *ahcf) */ ahcf->reset_sctlr |=3D 0x00800000; =20 + ahcf->sme_vq_supported =3D hvf_arm_sme2_supported() ? hvf_arm_sme2_get= _svl() : 0; + /* Make sure we don't advertise AArch32 support for EL0/EL1 */ if ((GET_IDREG(&host_isar, ID_AA64PFR0) & 0xff) !=3D 0x11) { return false; @@ -1199,6 +1189,7 @@ void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu) cpu->env.features =3D arm_host_cpu_features.features; cpu->midr =3D arm_host_cpu_features.midr; cpu->reset_sctlr =3D arm_host_cpu_features.reset_sctlr; + cpu->sme_vq.supported =3D arm_host_cpu_features.sme_vq_supported; } =20 void hvf_arch_vcpu_destroy(CPUState *cpu) @@ -1339,6 +1330,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) arm_cpu->isar.idregs[ID_AA64MMFR0_EL1_IDX]); assert_hvf_ok(ret); =20 + aarch64_add_sme_properties(OBJECT(cpu)); return 0; } =20 --=20 2.50.1 (Apple Git-155)