From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781131; cv=none; d=zohomail.com; s=zohoarc; b=k2QXpmDh3OvLec13FtZ+m57iukOYReyEbkptNoAlUM8wjYNRbyLnoHboLvAaGqf4PJRzLmzPSw6OGOtkXCSJpAoRhBm7PuXX5fHm8+p7TwY/jVT18C4mtwIfy5oCI+rTSLAsmCQ3iJswzOaKcQGKa7IdU3Hz+po552BdGuZQmvI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781131; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=aAJGv84Ss1wrOGywljZlC4+g4uy/tSqZFBXfSaBqFpE=; b=hrwQfOVrikEnTJSX8Pd6/fSGb1H5Yhtrd++vpAn4Z/aobsEWyS0OeFlVMDvpAYzSfkhspDIDZl8uJvMr2htgZ16YmpvM+3ci0rTOrrnEDwJSVGyCRcQBlDwGTyPm+0YUCFIQTNEmAgZonSmE+FCSgleHSR9X3u6avp9I5vfIZTM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781131859891.1359995316881; Thu, 5 Mar 2026 23:12:11 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLE-00038h-UO; Fri, 06 Mar 2026 02:11:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLD-00037U-Np for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:19 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLA-0007gg-N6 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:19 -0500 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-82989744ee0so1424028b3a.2 for ; Thu, 05 Mar 2026 23:11:14 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781073; x=1773385873; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aAJGv84Ss1wrOGywljZlC4+g4uy/tSqZFBXfSaBqFpE=; b=jc/IIg2aVUcdnPdbnkHLd33S2cHybUKKDcms3mh9GTBoo/w2TeY1sH6SpD8vpNS4HZ NSBPBIEbXnHoPF4i8DgBObq6+s5VmZ/4SVhsNPXFH4AWrrEqVFHBV7sT2QEwUmU3eRmM +w6w7ws+mp0AG+dXU8LQv9IrB0rGUYAo7bgkAznZ4YUAfCCePz3kOBj/TR8ybKuK7wCQ cqc+krkyqKlIl4+kKvCdW66jTndTdQ1OHg8xNtu8DSKRCR8Fm/SxUea9EoWRjPph2tGq kRabrhINW1YcbhaSig23J5zqMkHXnHleCnSZzPCovm687qpvJK2SuoaiV500s58OIc1r uXjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781073; x=1773385873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=aAJGv84Ss1wrOGywljZlC4+g4uy/tSqZFBXfSaBqFpE=; b=Bx/mHajjCFAaq1hC9E9+wYImthLJHsJ/f3yYlH8TKOhzw8vznGaUm9ro/6dbdC8QHk O5yC15w85JRTWJBM/arD4P+JqPcmoRf+J3M+tEgpoh1RBOLy7qGEgYzFAQosTjqMB9tn ziL+4LD0CzfEnByA7bpVBzXmfreC0jVnHfRqrfpLcBWiCy/hdamCuUFro10vxqjfJSm0 l8d2wOUoVRb1P5g5pMZ8+/XseXcBK4hnijaRwd8KghGbNcXMdeTT4PqEiGjZTHcRM4aJ QnuuKMWwq5ZT2El7Ag2LJiDO3DcTIsl5pBQhyRRZ8k68SzBueA8g/SPQkUBVQbpzJk9e fTuQ== X-Gm-Message-State: AOJu0YwlWvVDBdrDYXHgNH48a5mTkbUpmNVkYvxsBxoA4kRDUlOgVWUO OjQjMZXUwBP6CGiFL/UKfUvkT+TGYbxt5vOHUZCCds7RdZloGt4A/XA8ykVK9u3nfv6n7tFZsVF KiEcDqdVk1+Iq3u4spe/6PuceCBPQ+wy8yRWMigP0ohan3GjAsAzrvrzUDO340M9cCnKfmU4gEA uA9XA6zG07QXOYen/I0wS1Z5tGSDclzTrZFGu4wU9P5/7n X-Gm-Gg: ATEYQzxhQaP3yerTW9cDNRN58bijTAc5qQ0gYppzG4XCAi1jr1g8TQK3ID/bnFL7FnO 51eTrbwOh2iYaAo7co4wUv9Y9m5lQW4H6lJDEyWYJ/2sRKoni5bcBjxPm69OttiEO30Qm+63Jaf ExhGS6cbSGmY+I1GvFY634VfekuNwhnT9O67Y8ReN1pjBlOLTWnBMtge2CN9fcZnvNLpEfCnNGO MI1fqkmfEJsPBo6+SiL9LBZNbZ3/c5ag2x7fWSZ4twjOj8oRvUAm0SbPuQC6y2G2b6tf1z0F9iU /Rb/on1ChKopx+ACx3eDD2zsE64c6ojq+pFHQ22QI80rYusddBxfYhPWrHSUUwx/VN5wWx1Dzg3 iRR2Iw6Grp/uIBsuaP+xUHu8NZFpoAwak1TXHb18BGwVCGCQPvpkZgDblvWoMDKe+pyoC3JYfTI qJCt1JnMmJmcfXqa72edphDq9hLSGs4A2AQZ0a6cpCIU8t90O8yEEGEQwsSxeg7JeUl69GXq9A4 e1FgzTizPyJLufYcAnjZVx70Z4= X-Received: by 2002:a05:6a00:7487:b0:829:82f1:8bf7 with SMTP id d2e1a72fcca58-829a2d6e341mr861412b3a.11.1772781072930; Thu, 05 Mar 2026 23:11:12 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou , Daniel Henrique Barboza , Nutty Liu Subject: [PATCH v5 1/9] target/riscv: Add cfg properties for Zvfbfa extensions Date: Fri, 6 Mar 2026 15:10:56 +0800 Message-ID: <20260306071105.3328365-2-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781134529154100 Content-Type: text/plain; charset="utf-8" The Zvfbfa extension adds more complete BF16 vector compute support and requires the Zve32f and Zfbfmin extensions. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/tcg/tcg-cpu.c | 8 ++++++++ 3 files changed, 10 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9be79622f4..2ddc26c837 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] =3D { ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x), + ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa), ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index 70ec650abf..3696f02ee0 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -99,6 +99,7 @@ BOOL_FIELD(ext_zvks) BOOL_FIELD(ext_zvksc) BOOL_FIELD(ext_zvksg) BOOL_FIELD(ext_zmmul) +BOOL_FIELD(ext_zvfbfa) BOOL_FIELD(ext_zvfbfmin) BOOL_FIELD(ext_zvfbfwma) BOOL_FIELD(ext_zvfh) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 988b2d905f..720ff0c2a3 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -720,6 +720,14 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, = Error **errp) return; } =20 + if (cpu->cfg.ext_zvfbfa) { + if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) { + error_setg(errp, "Zvfbfa extension requires Zve32f extension " + "and Zfbfmin extension"); + return; + } + } + if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfi= nx) { error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); return; --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781178; cv=none; d=zohomail.com; s=zohoarc; b=Jtz2mgXplmVAXUNYQ1smOfKNvWbf6Wt3ANyFAqczpjcrwWRyOrMNhMulgKn94Cm1SOvBXRZL0R3m0X3ZbrCa2c9lysTN4q9q/AVbjP8/Tvz+GtKNCIWdaoC24d+BCR49fyxdggVtN5YXBZwA+fpHEWfg1oPEW1XZI2mxALUvWlQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781178; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9W26TJswWcNU4/2b2//AYfKIC4DULXqjlOY61SCME94=; b=QPJz0KhR1ZYfCf0cIaujxaNC6gMrwfUl0873/7hP8W89HsMCsRfZsARcfduapCFiPZyoPWmZ75KqXz9l/M4Vha5yhKows3ahiNnsj1LflhhCt8vQyfK983zw4KNq61cRyiTTP6zU4opoLdYlmu0RraQ4deh8oDUN4WdfvpY3O/8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177278117864824.363805734076095; Thu, 5 Mar 2026 23:12:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLG-0003A1-VB; Fri, 06 Mar 2026 02:11:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLE-00038U-MQ for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:20 -0500 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLB-0007gx-7W for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:20 -0500 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-8297c035d28so851615b3a.0 for ; Thu, 05 Mar 2026 23:11:16 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781076; x=1773385876; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9W26TJswWcNU4/2b2//AYfKIC4DULXqjlOY61SCME94=; b=lTw63FHAi+CImhqJ/tADDZQWTfhzIsY34G+fevOkCzY/v8Mmd6mn4/FwzaR+jbYNKx SZNGKzGnZ0Qjm3Hq9nqGeEs3kiLDfa/7YJFKJAkxWjIvk0P3FP3dknVGql3G56sFLOnR 3Nc/X049nV7x3TBYaVEiGd4WTSCYQXnii6ksTBWkngk5b78Sa0sep/aseGWLcz0CxeAp MTBytvKJeZIUjeAHpxMF1nmDjb1kekP22iTnTA/U5J9q5XhddV3F7ve5IwaUqyhSlG7r oWy0vWWkwOZrHfNjZjT38oZ7MxxLyPq3FTxqrZTyyF7oqI8s1eZfT6GEUaHagX8r9zay kTqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781076; x=1773385876; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=9W26TJswWcNU4/2b2//AYfKIC4DULXqjlOY61SCME94=; b=fgb3CdU7Wv8BH80ECJMjr0HHFYmhjjn01WgWABSUStWtQlH9jtULqTKXTtylXF3sXW mbl38gy+U+OwddFAQa6scKnr6nO/dW5Mjv8Ly4tZz/BB4CjFqxV/jSpqcKVl8A3POCDQ SRHaR6cwBwPU3NIc1F1/YbdOeggnGiAQl2hpiAT/xklNIDptzZMAxZblYtPeglVEKhOK LmIi4bmszMcCnzT02vcusX63x1TS8KPvMx9Dniqft7F4yQ+W4sO0nYjUjMx+deQxEHZW mHizpsX6Z/kkN/XJliCn3PL80FUvENAqq+YqNTE8OW5Uu5ig4IJDhp6AaTuXMVigvnzV ZIOg== X-Gm-Message-State: AOJu0YznlP2wfro5/JkWWLuwKB6Mgd+kZy96ll/86bLZRVi9HlHwIYie wI91qIEC9XJ7W1yGBQC+3bV9KXebzcWqQriT9IhTkcHOWx/ZFpsR+fP6iqzApOLL/nYM3W26/S5 h25AOSdebjH9RdrlF+r40CpP+VwwCsXoLGl+8hfp1zyz5/XhLnkNsdoZcZXgdWTdQ9X1so5y21w rodbLelpDAWK7tMnnJCxh5v4/f3rv0HD1LIPCaLpNlnRkC X-Gm-Gg: ATEYQzzS3VtBoJjTDYWsqzQZ2CAOWxzMi3kf8WJP+emo+9KaqnUP85Q3UCjkRKQyBfV cnns1+3fm0q65P1fqi86BntiuslMxN08gJk9IQIxxgm4tS9RrP/0rIVLThS0RNjPjgJ5WCYSBaq oAc9LKZnTEGgpdnQW8EIgsNOLhnd5FptWD+AcoOiNNiExKeidoVSAs6fl/xb+B4IR5I2LryZa8H AaCTcY2MK5raDKsrQ1aV5d45oJAD7DE7y9+QV2khXLv/WtgLFQs9tdlgPnVfurBhqGfUcV4m9/b f8z16WXwL9TZm8S9aBsg0L4nOgR4+ghcOCbfiAeuyfn+ReedfUD9EU68Q3bgK0HYBlEo63p0gwS XvC5YH6dym/SJ3xiteC7htpGhRq1kPjK+YaffgnlUtOsSjZq7SPTF+dvIcVtOYL1I0lvZFSl4bv jHRaLwWY3niFHOdA449w8Tlf/OTAPpf05oOkwt4Q9ci1+Rlpi5xNplDMxQVXUpjtr35LHQVMjWa uVb1zghWGMMjECGfSwKCgirULk= X-Received: by 2002:a05:6a00:6c93:b0:829:8fe7:7ac1 with SMTP id d2e1a72fcca58-829a30e02e4mr1045792b3a.66.1772781075514; Thu, 05 Mar 2026 23:11:15 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou , Daniel Henrique Barboza , Nutty Liu Subject: [PATCH v5 2/9] target/riscv: Add the Zvfbfa extension implied rule Date: Fri, 6 Mar 2026 15:10:57 +0800 Message-ID: <20260306071105.3328365-3-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781181008158500 Content-Type: text/plain; charset="utf-8" According to the Zvfbfa isa spec: The Zvfbfa extension requires the Zve32f and Zfbfmin extensions. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Nutty Liu Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ddc26c837..376517755e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2619,6 +2619,15 @@ static RISCVCPUImpliedExtsRule SSCTR_IMPLIED =3D { }, }; =20 +static RISCVCPUImpliedExtsRule ZVFBFA_IMPLIED =3D { + .ext =3D CPU_CFG_OFFSET(ext_zvfbfa), + .implied_multi_exts =3D { + CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zfbfmin), + + RISCV_IMPLIED_EXTS_RULE_END + }, +}; + RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] =3D { &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED, &RVM_IMPLIED, &RVV_IMPLIED, NULL @@ -2632,8 +2641,8 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED, &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED, &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED, - &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, - &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, + &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED, &ZVE64X_IMPLIED, + &ZVFBFA_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED, &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED, &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED, &ZVKS_IMPLIED, &ZVKSC_IMPLIED, &ZVKSG_IMPLIED, &SSCFG_IMPLIED, --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781165; cv=none; d=zohomail.com; s=zohoarc; b=C7w2tNWXZQNzjTKmZcwRWyLq/wnsjpVctRuhkMPUWLAOdLCTCzsixNf1EQgyktvfO5Q87D2xBqrCMNcIbs3jYsZqjEJvFTuZfIzVLyIAMaMuvlLUYBlCSyA758cp98x4gcS617xLBkFJBM0a9DFWvMOQandolYF9wTajXJ3AUEs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781165; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4uQDhR6YrGNT0dyapo0lViV7ZIQm3Tf5D9l0mN7YNH0=; b=Yqu/7c8x/ZB3s88rnZBFYEH1yGIBvSJzNAqsBgPi43X31GTs8/ZZMLbZUmvLbQ29hAXr9z12LGZ/4zOMPUrLEEzy7NbGqAnQolSkr090kAfHNU8gnZkoB5neKaLQztyovevhCoJUP17y+NdE/Ti8Y1Vtg7kEtSWpVjNumX3L1nY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781165565849.2699267887435; Thu, 5 Mar 2026 23:12:45 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLG-00039u-Fv; Fri, 06 Mar 2026 02:11:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLF-000398-B3 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:21 -0500 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLD-0007hg-Hp for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:21 -0500 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-c6dd5b01e14so3172542a12.0 for ; Thu, 05 Mar 2026 23:11:19 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781078; x=1773385878; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4uQDhR6YrGNT0dyapo0lViV7ZIQm3Tf5D9l0mN7YNH0=; b=A3g3kqMPNWawPmu7E7cCSboWK5dY6Y667ctBGq8xV5AX45uGFpLSnMm+FqGOOEdd0k LhsyRh7rw0pFtvuJYsDs0t7RwPJt4TjMGKTFtzYnTwLZCROpq41roEdmX7dmroeABw3f 2E8yhMJn4ekPw1UkcTrJiBo3DRgqsiqBfHKI33lpDuK8OMGQH8cnhnVY1t48DJxzX3Cg widGLUeoUo1KSS8CQlqcUY+Da1vYzmL1fVzNxHnYWYYBZ4RoPmC7/fsAEsl5HzOHRcd4 uCdNm2ghqRb0ttwJDx7Fm1/kYLCVJ3QyDO6bY3xOOq9MZDtr7PqopqDMDpgSuxL7eiph yODg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781078; x=1773385878; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=4uQDhR6YrGNT0dyapo0lViV7ZIQm3Tf5D9l0mN7YNH0=; b=IIsBqxjbMDv3AogLaOSHScesMOrpoG4G0JMWoNa3R0PNfp+gchZyZkAEOq6FokVurr dc6PjbdhOc0VvnYmfnU0SyaF+NYEeBiyujELFyMSBQHNoALiQBCTgLgS0nqjo2rjhUpv PpZjXUKh3LSGD8Pa2c90BgJwmQLPfFG4udW8tpMobCsPzLVz8wO/qjzNZmO/NfpkGLqq RDc2cu10zPFRXlN5WhEB9ONiv1q8Tmu5NN67vknGmal8+uPLLfIoleF3fNmypyOsC4og WInaVmaQepsAavS0Mwh460+n6rk/V0BVCn+Mhl8w8spzgoixixy9fEcI1O/9Ks2AAD2+ kOKg== X-Gm-Message-State: AOJu0Yxu3kVbLFamIp/LYK7jmj8DIZpiP/kv8tu9uVVwtfd32gqezrvv VnowocweOGzIRfKxUadjE+lHzp9cfHPcdAlia1TfvD6zjTkNw4BA8wQ6pfyIyabk0UJeL+k0mkr QXX0eWWNppBvN1rSfnpbhha0UZA1rwqeM4e8Zd+BLwfGndvPBwiAaUYMSCb2327rPutxE2kqHGZ a+aFUV6jyXVufAk2Q1kW/K/xmPjMrNWkqTesX7xZUrLyEC X-Gm-Gg: ATEYQzwin4xwHWx0J+EKaxnvjzRNQHu+jA4vCDLM1/ktE9BfpfGTYlhgOLhu84Rfhzw tvPE9YQCZWfYGJNcYvvvRGtjRigBGFQclLicPdtRDwG6z06CbqwoBCQe69P3INhO/QSoJ2akp8g RBH2VfSgPnsm7V0KR32HfrDxXUKDw/rTVGnZ4cM1zUJfOB0NE7PBlGLEj0ziZc4twrgY/0+xay1 a+Nro9GXlZb7OVeewEAWU61r1BXQ9f6ABWrJaxVZxLcB8Mtd1IgsoHHHOa3v9sNKulz9pWtNZJr I83n/2H0Wmts20kpusIIHIfhszteMwzuy+nOyqNwyF6hEvTjXlRyw2mtLjpnPlijAIFf8a87Tiw sKR4kfKYdxKDNH3YqMpfU0gMgT6wKaV0C8dShtUXfwigEXBgxyZ2tLOaEPG0i5wfWs8I8FmBFmZ HEZzRwx2jlvS0Cikl+znzJSR1DVYuZZbrP+vDhRrUVFvUTiS4ArR13aOC6Fn8I/gNIZUIKFNmbf oyLJ/pTLuEJzEMziLY2zNaxOaI= X-Received: by 2002:a05:6a21:700c:b0:398:4a20:cf90 with SMTP id adf61e73a8af0-398590ec6d3mr1466218637.68.1772781077877; Thu, 05 Mar 2026 23:11:17 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou , Daniel Henrique Barboza Subject: [PATCH v5 3/9] target/riscv: rvv: Add new VTYPE CSR field - altfmt Date: Fri, 6 Mar 2026 15:10:58 +0800 Message-ID: <20260306071105.3328365-4-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=max.chou@sifive.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781166852158500 Content-Type: text/plain; charset="utf-8" According to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field: altfmt for BF16 support. This update changes the layout of the vtype CSR fields. - Removed VEDIV field (bits 8-9) since EDIV extension is not planned to be part of the base V extension - Added ALTFMT field at bit 8 - Changed RESERVED field to start from bit 9 instead of bit 10 When Zvfbfa is disabled, bits 8+ are treated as reserved (preserving existing behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+ are reserved. Reference: - https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu --- target/riscv/cpu.h | 4 ++-- target/riscv/vector_helper.c | 39 +++++++++++++++++++++++++++++++----- 2 files changed, 36 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 35d1f6362c..962cc45073 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3) FIELD(VTYPE, VSEW, 3, 3) FIELD(VTYPE, VTA, 6, 1) FIELD(VTYPE, VMA, 7, 1) -FIELD(VTYPE, VEDIV, 8, 2) -FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) +FIELD(VTYPE, ALTFMT, 8, 1) +FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10) =20 typedef struct PMUCTRState { /* Current value of a counter */ diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index caa8dd9c12..7575e24084 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -33,6 +33,22 @@ #include "vector_internals.h" #include =20 +static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype) +{ + int xlen =3D riscv_cpu_xlen(env); + target_ulong reserved =3D 0; + + if (riscv_cpu_cfg(env)->ext_zvfbfa) { + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, + xlen - 1 - R_VTYPE_RESERVED_SHI= FT); + } else { + reserved =3D vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT, + xlen - 1 - R_VTYPE_ALTFMT_SHIFT= ); + } + + return reserved; +} + target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong s2, target_ulong x0) { @@ -41,12 +57,10 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, uint64_t vlmul =3D FIELD_EX64(s2, VTYPE, VLMUL); uint8_t vsew =3D FIELD_EX64(s2, VTYPE, VSEW); uint16_t sew =3D 8 << vsew; - uint8_t ediv =3D FIELD_EX64(s2, VTYPE, VEDIV); + uint8_t altfmt =3D FIELD_EX64(s2, VTYPE, ALTFMT); + bool ill_altfmt =3D true; int xlen =3D riscv_cpu_xlen(env); bool vill =3D (s2 >> (xlen - 1)) & 0x1; - target_ulong reserved =3D s2 & - MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT, - xlen - 1 - R_VTYPE_RESERVED_SH= IFT); uint16_t vlen =3D cpu->cfg.vlenb << 3; int8_t lmul; =20 @@ -63,7 +77,22 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_u= long s1, } } =20 - if ((sew > cpu->cfg.elen) || vill || (ediv !=3D 0) || (reserved !=3D 0= )) { + switch (vsew) { + case MO_8: + ill_altfmt &=3D !(cpu->cfg.ext_zvfbfa); + break; + case MO_16: + ill_altfmt &=3D !(cpu->cfg.ext_zvfbfa); + break; + default: + break; + } + + if (altfmt && ill_altfmt) { + vill =3D true; + } + + if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=3D 0))= { /* only set vill bit. */ env->vill =3D 1; env->vtype =3D 0; --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781220; cv=none; d=zohomail.com; s=zohoarc; b=Yco5vdbQ8KA3UJ83DJZeBZJnQfp+MkKwoO4RhvP5jfhjPNGkANfC41r0hwZLk7UEA4iCDAa316PTrQ6CzVvKvdDCNuvD0Ttp9SOlEOIa+TNdTK2+AuS/DIXzAfd0ktX+5wa0td4AYdWLgaCYUMdaYeQ46hwQZYlzHEzWbEfwp/k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781220; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=XHny1TMn5q5In1DNoCgSGzLeh6esAvW3TWT30T8JNEo=; b=XppaY0trs2Bko6+4YNZKWEEec4SE4olmQHB6tyrxfsuXY0G/9fvtUlFsYtDw4Q+L18+uV/8XjOPTkSYqw6kvw2S4+3IFIEe9soBqN1qr/Gxe+F6eJKB+tenRdDgL8w21vhOAzdA+injtEoUMmmuQx5Mtj755KamwYpm2s9UO8yY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781220603408.5875631298393; Thu, 5 Mar 2026 23:13:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLK-0003Bx-JO; Fri, 06 Mar 2026 02:11:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLI-0003BA-PF for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:24 -0500 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLH-0007jC-54 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:24 -0500 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-827270d50d4so9274935b3a.3 for ; Thu, 05 Mar 2026 23:11:22 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781082; x=1773385882; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XHny1TMn5q5In1DNoCgSGzLeh6esAvW3TWT30T8JNEo=; b=Y2J6xUsssTE/KwerY5DUtTP2rhMsgnjQL9qIxavLHNl2SbzrHDPBpfKBqjwXB1bAYz DPu3GnQHKb3o/JB1avMT2sDg4pl9IFZpz4RlwYDmGv75OzvTzpV+rXykenvlCzSho5o/ Cvra+/hBNYYpXk6cUWfHg4Rmh+gmqU8q27VoKTDuhrj3Fw518gue/Jf/SIkhd+rYu/3V M1+zBx4PluaZIUpXEaVSR+s0koxjEUZ0fUb5XSSc26mpGwV1NNGddqh21567+Vfpyj5I kgq34KNsleC3zHofxVZWg06Xl6+WlgbuBOTsQP+Z2FzzvsbU9XukFAZ4nVGzE6rPMnxF oRSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781082; x=1773385882; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=XHny1TMn5q5In1DNoCgSGzLeh6esAvW3TWT30T8JNEo=; b=Vq9OYnYEQLeIxjIyaLhCvDlKYfDqfz2p+m+1Il5WfjAWmdNagnCf/NBQhV3QvShr6H IbKEncl2Q5yZSdElT4l4d4QvQxSkf69NAroh3/t4dE6iQ572wrPavW0VGhTqslTCnysH HyIPqus6f4asNqJvRXBlY5HOUdtrc03L1qAmstTBK76uodRkzF3RPCPpCvgJDW2526OB 9i7Z+RuSJm84tZBHii7gMCOvtSmWITpwOaj6qQKiPDLYamww6RuTvTShWgKdLbaI2K7p cDtgNTDOb2B8tmftwrUkI3sRqDzEET8cL1FfDe42h/iod/SxPAQwozXeIIqaZaVwJwUH b3Lg== X-Gm-Message-State: AOJu0Yx34hVRuCYZA990qeFRQY+Jb8eGoAhw24G5MlJW4PdujbOQ1nRL B0z5AfmhY16v3t/lMI1KrVGj0xx0Vydd8NNSPIi8yAmcMgtR+JJjs75//u1iZIKs2r3QHWNR+M5 vwiD8TxYul7VCCB2KWBhp+sZk1hf62Sfm1wUX7/I7+fQzws0v2JyoQ6pLtzkAAwfQoQ+rvo+Mab AxTt/giKJVFA1XhXaRM+7xIdiU/f9J9EOaCAT1UvRZViUd X-Gm-Gg: ATEYQzx6+uyShJZO8MPsPAPYAxlBs6wEO0N+8yF+cDqB1aRXd6KB2EyxU+QMOgoLqWb Ql3/HgCUgDDJ/T7ujMEL4nbCAf//oWCahpqttZXX7QhNK1nvdJBpdg/XsHKGTpLRc/tUoM8iof1 u1FClnTaOrXF1AQfsfpff8NgVHAynFVURh94uCY/Aif+XHHrNPRxKILzOhm74gbjx5o1WkuOLip iZwJwpq6KW0YMXF6RCVIYyV3vo0EjnbkSMPQsrMQjPmF9jANjF378dhWr2XZcRHeleFWE8+GARy iNgCoaTMFXjSH8If4ERimKIUOtpgxYCU2pd5rgcEVWhT1Z3LeUc5yqRssLNqX/Lf+UPA9JViTtk OxASqdPUV0wan6PIVxoem+HdnBjzWitVZ2HcmlMRuWkoROoKekVBCb/u4/S25Yn80ffAmqdHSF3 394/NwMqfE8rdx8lC6BpL1AKXxW9gzqgIwVT1baIjRdQ8AiWVhcV30q2wYz08Bf5u8UWZbs2U8X q4PuAmsPmpdkKpDy7pngwCjttA= X-Received: by 2002:a05:6a00:1905:b0:81f:5f49:6913 with SMTP id d2e1a72fcca58-829a2f788dcmr1144696b3a.30.1772781080006; Thu, 05 Mar 2026 23:11:20 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 4/9] target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype CSR Date: Fri, 6 Mar 2026 15:10:59 +0800 Message-ID: <20260306071105.3328365-5-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=max.chou@sifive.com; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781220903158500 Content-Type: text/plain; charset="utf-8" Replace the same vill reset flow by reset_ill_vtype function. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis Reviewed-by: Nutty Liu --- target/riscv/vector_helper.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7575e24084..b7105627ed 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -49,6 +49,15 @@ static target_ulong vtype_reserved(CPURISCVState *env, t= arget_ulong vtype) return reserved; } =20 +static inline void reset_ill_vtype(CPURISCVState *env) +{ + /* only set vill bit. */ + env->vill =3D 1; + env->vtype =3D 0; + env->vl =3D 0; + env->vstart =3D 0; +} + target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, target_ulong s2, target_ulong x0) { @@ -93,11 +102,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_= ulong s1, } =20 if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) !=3D 0))= { - /* only set vill bit. */ - env->vill =3D 1; - env->vtype =3D 0; - env->vl =3D 0; - env->vstart =3D 0; + reset_ill_vtype(env); return 0; } =20 @@ -113,11 +118,7 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target= _ulong s1, } =20 if (cpu->cfg.rvv_vsetvl_x0_vill && x0 && (env->vl !=3D vl)) { - /* only set vill bit. */ - env->vill =3D 1; - env->vtype =3D 0; - env->vl =3D 0; - env->vstart =3D 0; + reset_ill_vtype(env); return 0; } =20 --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781165; cv=none; d=zohomail.com; s=zohoarc; b=AtoVhdVfoEoU38nFGPmgn/eIexUr8pEbsR/Dp+oLNv+voGpwhJkimEdjso1mDscrfZtscYLif23iW9hhQ2NDpFufJOx755idpPFjCx6y6aZlo0OH2iliJ2PPp6UCgV1Xo3F8NcF3Y8nZnu/10nJ3KqH9yHNGJfg1ZsENnLLY9b8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781164; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YwkyvuFqvL3DmB3RXIctZctihtn2i06JRpc/WAF1Vhk=; b=ByGQkC548vMRUWplYE7ZXhDlB87HAzTcI8FioFQMX5R+rgcgdJuornIngZNqyWZEAX80UZtfdXpGoOoBluXef4Cl5WVL2HGQFYXQhXFRSUK2QhpSRebOxNTn0vJinKN0QacaHon2t1cYuY2rIaUMYF7s1XEo55e++dGhdpIvPDU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781164878916.4535432192572; Thu, 5 Mar 2026 23:12:44 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLL-0003CB-EJ; Fri, 06 Mar 2026 02:11:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLJ-0003BM-OC for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:25 -0500 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLI-0007jl-2f for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:25 -0500 Received: by mail-pg1-x536.google.com with SMTP id 41be03b00d2f7-c738aa3cbbcso1206606a12.2 for ; Thu, 05 Mar 2026 23:11:23 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781083; x=1773385883; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YwkyvuFqvL3DmB3RXIctZctihtn2i06JRpc/WAF1Vhk=; b=U8R9jJcx6rVyWcxHx83DIfoyBldIIzNkStSAvlITKwD+snQhZDuuXmrWGSIcsWosZF aEpv3cAwC6RTyixIItoHQewMJX7Motb8u++EFirBaTkxPDbTghOWG+0XL8mudyoaeh+y dqN4rR0sTBN+1Rz5y8vGIlqeO5QQK2hDTCSbPCvg750bniwRzV7VWqTN6o+1SnX9IUof fjuVG7UYAnTwofIBgPQMNeLnlFiiDBX18JLPDFICssnLAoAtpvwWxtpuXGCSQbk7XM4Q Icg9OP8XmdR+6/O647nBsYYtsnkEsvlOrp8kGHDNgqPGZnBAInSBlPcY02a0FIgppbZ5 wMjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781083; x=1773385883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YwkyvuFqvL3DmB3RXIctZctihtn2i06JRpc/WAF1Vhk=; b=ZWhXa0xlQ3UMdbrYPfznMuDew/GHDg1TfrSYnLYTSv7IkN1JZe/+tk1+uZrpcRmLTs MtaddqjjiDy17woa+Z7ukRLa9RNq1jT83DeyL2OFQguRrMhczKDTmBvzezBf/E1znTZZ +xGER1pXPMMJqa1ogKPeKfYR3RzMsnmb7JYnHm1Q83r0Ms1TqJ8Z8rJwXND957M4cdFw EZx59BuKiAbUwJB+pBLWynohKEzCQQFQ8/bnZw5R698PfXPfK259L8OadZhA3QqEJFqZ Mw17xwc7X4fm2uPKdRtJpSXxzUgGytuDS3/IWlx4Wgryvec05YLCQQFO+5zH46F7lXgU DCjQ== X-Gm-Message-State: AOJu0Yy5uCcGxSCyvvMHItauhix7syChs47L18Z4NN+ZRRzaJ7t2MA55 3LE9HDcoWyow5P6iiboeSlc1OV545vQnBuFovxnkiPOw1MvvvgaXuI+9M2ZOc0tFbIZPos6LNdj XeGrIXGrrUWDA2+z4PCevet9uVTl70iuustDyyB8/DkhAAL2iP/+lu/3B6MlHr1ZH8D2SzKhcVU Cy0zt7lXGRH8NUOmTmm4FhhJAw0hsxqrJjE7YXFizE5Sdh X-Gm-Gg: ATEYQzyBk6LQo6OIUs1DQ9fex8h+Plf+G65coQM1Q0ELGLUvflEVhDDTClv471qor9d DeOHjcyul04Hs0bnL8c8DLllnJoL9J9vLTuXju3dcR7Rlqs8coFi2iHQQRlsZnHyX4Ib6DuK6bx 38/qoq8eIR7J9mNknCtSct9088ghzG16ZLMxznfn02bzL47xuydE8YRFOrn78t7KEHZ8KJp9tNM 2rtXKfyzMJCM7AoLnLDFf11aSupWXBuH2Qg+IckaqRdFNHoArrl85MWLqmHPQKVTDdotEMAnZ3E h1gm5+M1Uvf/4pUdGyDCeECXZjKZcXY+DgUD8pcDGnz8EzNb7F1wSK+B7so96KzX6SIXlowPCYZ uynwl/LaAPtMP2P/LcUHDcARz3v5fJvTbFJMQhyFCtIDlIv/vbRfljLaqUlxpOMzx51SdZFtA0x OrMA2fhCFFwiRehYm4xPctoOBdCObAC5945F3uLGaTnsm4CtIwSpMx5GPV9r+8jOuoHruap4ppP OR3GnKEx0SCXtpUHyLbDq3QoU0= X-Received: by 2002:a05:6a20:cd96:b0:398:4af5:9e04 with SMTP id adf61e73a8af0-398590d65dfmr1324100637.68.1772781082298; Thu, 05 Mar 2026 23:11:22 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 5/9] target/riscv: Use the tb->cs_base as the extend tb flags Date: Fri, 6 Mar 2026 15:11:00 +0800 Message-ID: <20260306071105.3328365-6-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=max.chou@sifive.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781166848158500 Content-Type: text/plain; charset="utf-8" We have more than 32-bits worth of state per TB, so use the tb->cs_base, which is otherwise unused for RISC-V, as the extend flag. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou --- include/exec/translation-block.h | 1 + target/riscv/cpu.h | 3 +++ target/riscv/tcg/tcg-cpu.c | 7 ++++++- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/exec/translation-block.h b/include/exec/translation-bl= ock.h index 4f83d5bec9..40cc699031 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -65,6 +65,7 @@ struct TranslationBlock { * arm: an extension of tb->flags, * s390x: instruction data for EXECUTE, * sparc: the next pc of the instruction queue (for delay slots). + * riscv: an extension of tb->flags, */ uint64_t cs_base; =20 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 962cc45073..4c0676ed53 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -703,6 +703,9 @@ FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) FIELD(TB_FLAGS, PM_PMM, 29, 2) FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) =20 +FIELD(EXT_TB_FLAGS, MISA_EXT, 0, 32) +FIELD(EXT_TB_FLAGS, ALTFMT, 32, 1) + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 720ff0c2a3..378b298886 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -104,6 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; + uint64_t ext_flags =3D 0; bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); =20 if (cpu->cfg.ext_zve32x) { @@ -118,6 +119,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) =20 /* lmul encoded as in DisasContext::lmul */ int8_t lmul =3D sextract32(FIELD_EX64(env->vtype, VTYPE, VLMUL), 0= , 3); + uint8_t altfmt =3D FIELD_EX64(env->vtype, VTYPE, ALTFMT); uint32_t vsew =3D FIELD_EX64(env->vtype, VTYPE, VSEW); uint32_t vlmax =3D vext_get_vlmax(cpu->cfg.vlenb, vsew, lmul); uint32_t maxsz =3D vlmax << vsew; @@ -133,6 +135,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) flags =3D FIELD_DP32(flags, TB_FLAGS, VMA, FIELD_EX64(env->vtype, VTYPE, VMA)); flags =3D FIELD_DP32(flags, TB_FLAGS, VSTART_EQ_ZERO, env->vstart = =3D=3D 0); + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, ALTFMT, altfmt); } else { flags =3D FIELD_DP32(flags, TB_FLAGS, VILL, 1); } @@ -189,10 +192,12 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState = *cs) flags =3D FIELD_DP32(flags, TB_FLAGS, PM_PMM, riscv_pm_get_pmm(env)); flags =3D FIELD_DP32(flags, TB_FLAGS, PM_SIGNEXTEND, pm_signext); =20 + ext_flags =3D FIELD_DP64(ext_flags, EXT_TB_FLAGS, MISA_EXT, env->misa_= ext); + return (TCGTBCPUState){ .pc =3D env->xl =3D=3D MXL_RV32 ? env->pc & UINT32_MAX : env->pc, .flags =3D flags, - .cs_base =3D env->misa_ext, + .cs_base =3D ext_flags, }; } =20 --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781216; cv=none; d=zohomail.com; s=zohoarc; b=Lpi0zonwEtCbY/p7yr016wigmTBbl7U8tUJyGbIQqNtiMm4eztIv3gvK4fdlCJV/Kr4Y7cs2kOYOST+lzeQ73byrsaa9SIiFzZ2m6KnvGncEABsHLqW+gfsyzMBzBALNu0F/8DUEtggrjOJzZZ5jnNdkxWPNDKn2NC9Q8wIb51Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781216; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7M4+raLDnlsy7KZxdfXOt2SaMfVSiy+jv/eZ9IfwtZI=; b=KjZLHpJ+VW8TPHwYOHAm/xmcLaHzeMCyjTsVvBgzb39MdlzV9rP6+zczyh2lqoCHp0fbmjDO3Dq8qKWvqnT69TE3pj4zRJi01EGg3YpnAjt7pRD+GXc6oOEarV3xlfT6vDUxTfDK/r/ZWN+ZvYyjp5hdPl30d+bmGuYz6S7kmwA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781216027693.4866038905549; Thu, 5 Mar 2026 23:13:36 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLN-0003Cl-1f; Fri, 06 Mar 2026 02:11:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLL-0003CK-T1 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:27 -0500 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLK-0007kU-Dg for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:27 -0500 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-824af5e5c81so8839379b3a.0 for ; Thu, 05 Mar 2026 23:11:26 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781085; x=1773385885; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7M4+raLDnlsy7KZxdfXOt2SaMfVSiy+jv/eZ9IfwtZI=; b=WvyPgzqd5s8HMzale2YE8Kit7NbTygCAWf40qdzE224Bfpp2qfBy/QvRV5N+KIgaXV C4WtPY9kDBFMjA7jV7yI5BRakTXw++tJRt0+2ojhvB0c+U1f6q3hPBnf6JFdSMDN9YbQ q3tCR2Yb7AO9CpPjUJXPo+8T2OeoNroyo0DF24qFp/fNOzhNt+fMxuAu10f1TKkudeUM aQ91ecyVzmGXIo0sr/RPRQFkVWFluxXPDBc4LOSD06O6svVvOGcYR8YyYJXVYut/PjDM AVSyDEhAWkgJ7Sg5WppWG+HSR51b+LPDmbzgfZecF9tY5FxH8Hp47rGGfEqmJcOoR84V DJhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781085; x=1773385885; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7M4+raLDnlsy7KZxdfXOt2SaMfVSiy+jv/eZ9IfwtZI=; b=XfzBpbIEtOMjuGqMLeAkxvzcEcAT51nwfGfm4ekPjsZCe4ZH/bX8XsoJh+3wdXRu4P PWn3Ndl14sixUA6asSb5RHwC7lYhNXsJkgMsUwGixS3rQmOCm6KjiJ8sFwqH+rlUMwSZ IRKYlGClqFwfnEYYMqQP5sJ4yCJuEfAmk//DOXlCeZCBUHpyrmDYmUDGuCduQ1/gVkrf nJ8gUytFIUR8ImmeDXlmZYu6/h+RfWOpNFBx7ur1Z3wfNBIQEQABml8vLN7ks5luGBjB VCI7ZZzW9Nwv0PshB3W5YMvQJUbHm8DzDNpiS2DuHb024hVeQCqitxW0SoakRcS0lokn nS1g== X-Gm-Message-State: AOJu0Yy3KVa1QE8M92ka1lSiciFdmsSYwnMa8pPJ0zHsFd3hNT9/LUSS O7Y+x4ycGvcD36WNAMLVGJKvbN3AcXaRRiBjkV4uL3aruYqxUa78Yp3G2lT+xYHnvP27bLNMZIw WNWvVlUx+kMY8epNkvuUN4OKmDfYxdd58RzDo+/Qn1XPM47f9YztZgxre8fIAP1Ga+74C4bQxZe kM/tmS2d1CJ5CfKQE+/+5uU17l/aZXMKtr7CQbngYCgjhc X-Gm-Gg: ATEYQzyMRmbwHKQEW3qH0J1ZA3msQnD9YGW3d2r8JOIBeVQhpSY2cbJ31txYfJPpcPA Wb7DG1R8fJzkZajGrgGx8PEefaydKSBNXMMMcJGzKuv1BZmlE3Aqgj7JrN/CMUYr642RJ75gukJ xW1rESXNOUnt4wy8gnIClW1BInYrMsryP8pO4y/wP5oYjZbqJHTmaFCezGBkGUL+rIY/fkJxdJV zcunaASwjoAnhG6SFyZTZY+RMciK7J4XSBYjEba0KTyjsSedFhOHliJHoLuai9X2u/vdmAaQGzF mueqendM6/zEakJPOoRYrwOC72l3DvMa1PzyrqwZicjPr5/aO6U81ZlrtK3F4CMm2QJRBlbez16 KKFGWDxZ0Vw5XBpRWmypmx/9tgFXtJj5gPPh/6A3aDbIPJMQMt9WjFMcRIR4d72+46GXsxxdbW4 IoJA/r9kbOFMlNkmVH5c25fP8Y8ScmC8EGPzmJcnRO9DHKgSxKg5XaAhPlaElexjV4pDyCDMphH eUe/R2QRbeHdsUJYMAuI7A5/xo= X-Received: by 2002:a05:6a00:1408:b0:824:93e4:2de1 with SMTP id d2e1a72fcca58-829a2eaed31mr1140486b3a.30.1772781084799; Thu, 05 Mar 2026 23:11:24 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 6/9] target/riscv: Introduce altfmt into DisasContext Date: Fri, 6 Mar 2026 15:11:01 +0800 Message-ID: <20260306071105.3328365-7-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=max.chou@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781216932158500 Content-Type: text/plain; charset="utf-8" Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cb4f443601..89d4f6fe67 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,7 @@ typedef struct DisasContext { bool cfg_vta_all_1s; bool vstart_eq_zero; bool vl_eq_vlmax; + bool altfmt; CPUState *cs; TCGv zero; /* actual address width */ @@ -1307,6 +1308,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(cs); RISCVCPU *cpu =3D RISCV_CPU(cs); uint32_t tb_flags =3D ctx->base.tb->flags; + uint64_t ext_tb_flags =3D ctx->base.tb->cs_base; =20 ctx->pc_save =3D ctx->base.pc_first; ctx->priv =3D FIELD_EX32(tb_flags, TB_FLAGS, PRIV); @@ -1326,6 +1328,7 @@ static void riscv_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) ctx->cfg_vta_all_1s =3D cpu->cfg.rvv_ta_all_1s; ctx->vstart_eq_zero =3D FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax =3D FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); + ctx->altfmt =3D FIELD_EX64(ext_tb_flags, EXT_TB_FLAGS, ALTFMT); ctx->misa_mxl_max =3D mcc->def->misa_mxl_max; ctx->xl =3D FIELD_EX32(tb_flags, TB_FLAGS, XL); ctx->address_xl =3D FIELD_EX32(tb_flags, TB_FLAGS, AXL); --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781201; cv=none; d=zohomail.com; s=zohoarc; b=e0kTBNosHCZ7stmnaWmW0xpHeam5duACmV2tZsQXF3PKwfqX/m9JVTUuZLKgnrXg2ulRZeAo4TQ07uX/tTitt0CQL/yCqYSxxC+BLB2RQNToysRKE1Qp2ZNtJFC8T/Wvnr9PrlSKnHU0fBbnSp6vlry+q0svd7/QLk6wKqzY/b8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781201; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kt+rzQ1UgiE2GK7Z5HkdPPR7yZ9vyWBgUNG5GVXze5Y=; b=gFnbxJHDES7lruT5euF+0IZoaxRtGZK5XI6auHgd3hsHQZNi0TMNRGYCZ+zxrUeUIji94ukXdBs3E8Th6cfCz9pKL4pnsPPzHsgi7yQWHXjfKaEPoXTWaeDUo74iJKu97jlawCtWK3BGK0jbiDFWrvLz40z/YC/OWgH4DL/KAis= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781201282486.16841876927936; Thu, 5 Mar 2026 23:13:21 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLQ-0003EC-Cf; Fri, 06 Mar 2026 02:11:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLN-0003DL-T0 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:29 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLM-0007l2-E7 for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:29 -0500 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-82987437624so914138b3a.1 for ; Thu, 05 Mar 2026 23:11:28 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781087; x=1773385887; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kt+rzQ1UgiE2GK7Z5HkdPPR7yZ9vyWBgUNG5GVXze5Y=; b=CZ9pABvZ82Ix1PsePRhZHIG60HnPfATjvP4UPXHinx7ubxJqcA+os6zJTWJGRaAZvp INDNrRKNf/kR5btJHto7dYDizJ2P1WoBtrH1F8LpDqmbEYOhyCUT5GgbjTTP6i+ZKwIF BEK/awtspo425kGlWiaQ3tvjO+y7yp4y2Q8WhFkdHNaY/CltO9bAOE5ux9u8fROHH/cU /f/HD2DPu9GPV4wzf8a0AP2mBpIcN3q4LboJdCfhocFB0xqft2CtSq6x6v+CPfy0FqVF IX4S4sASFyoB2aNVT/6+BlOLShg5EUovzH0TASCFwahaSSIbPb/9ft2dfXUAjtjQLeYT kPtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781087; x=1773385887; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=kt+rzQ1UgiE2GK7Z5HkdPPR7yZ9vyWBgUNG5GVXze5Y=; b=SO+AZ79pDa7YWgNl9QLY2X07YpKGFSL8HL7NTIhmwlba3UVXzn0CYdxradkkGyH0ka t0JyKjjehfIC7p9vAQ9OpY7VW/2pLnZWskGbKPpYBploFCHHkPvdw2fhad0hrg6aqEko hKL9lZk5r6/9tbVWS7akCxiXpqSEP/MLpO7pdFH/iMG78BoqQZTqAnEpOERs9vYQTQCr Rl81sWCHLyzkioilEwpH/DJ64I81LblfRDswHi0FnhZzimeVc1si42e5X/PeMayuuG5I FlK2XOWURN1Edb60USQRfTOmPSmu8cjKoj3MEO2VxLeiUcMIKKzp/krWOKvoi8BFAoPC vpoA== X-Gm-Message-State: AOJu0YzZ46fTEwADylhuyecWYNABmS305DOruo5+MUsgl32iBaxIGZkw Ws2uS7r5ad9N2lUI2OaAf8rykXX/xm36ZikOM12v9Yfa+6DDqt+NVBa+Nbg0jJKJRM86fJtvyfD NDDrBD/NZ2KELMiklIZSoYebOkRfHa4tx7K1CqqENahJEZ7FoIg0vZjifZ00U8Wd2t/Aj1n7eT2 InNX9W+0vCNBSSI2pj9NWC3aM5AN4DVewrvHqaS56+wdPp X-Gm-Gg: ATEYQzzTkaCRM+ZJy6jnDjwgcAvTHGq0lvtmtAxCSUlstf31P33MUP8pqZYbcCFgyM0 c6683td6bx49hQE+3fMbECM6ZCn9UNEPvD3MUh20QTp5IMD4jprBA1pJy3JHbPGBMnk97ce0c4X LL8NuXv5bNwRM5fIRcNYVTOJ5oK0tvc/yz6I3V9g8UINNxWnNScD2RqngDYE4WzzptxkWwtu4GI LV+CbuZIl+DtqN3GU0iyh9KhjI7ksuSqR9XUOWL46EMz4pz8eM27w5QcGZBk/lSbsChLIg7p59V O1GNry0sIxCtTzESDikAR5EXLMBDC1+LvrAV3EOywJHc4ZVEXvE1w42ao2NInXkWHoQxxKZCk2R aoTWBkHai3OEAldHUNxZ+vznliCkn35SInvCcbREyDgEfl7AD9cNYKU1evKsvicxUyVAptIEHbu wkmrpq5Rf1LkNP5biwChpIifqIej6Hvnh/gIaxuYKiU2m5uJ0Aj3znSraokli4RLoVNaJNBMNQ1 zasFAQGX/M9P+VALXy3PASgayY= X-Received: by 2002:a05:6a00:2ea4:b0:825:2927:3aa6 with SMTP id d2e1a72fcca58-829a2a12265mr1353647b3a.14.1772781086983; Thu, 05 Mar 2026 23:11:26 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 7/9] target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension Date: Fri, 6 Mar 2026 15:11:02 +0800 Message-ID: <20260306071105.3328365-8-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781203464154100 Content-Type: text/plain; charset="utf-8" According to the Zvfbfa ISA spec (v0.1), improperly NaN-boxed f-register operands must substitute the BF16 canonical NaN instead of the FP16 canonical NaN for some vector floating-point instructions. Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 18 +++++++++--------- target/riscv/translate.c | 8 ++++++++ 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 4df9a40b44..03ae85796a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2319,17 +2319,17 @@ GEN_OPIWI_NARROW_TRANS(vnclip_wi, IMM_ZX, vnclip_wx) */ static void do_nanbox(DisasContext *s, TCGv_i64 out, TCGv_i64 in) { - switch (s->sew) { - case 1: - gen_check_nanbox_h(out, in); - break; - case 2: + if (s->sew =3D=3D MO_16) { + if (s->altfmt) { + gen_check_nanbox_h_bf16(out, in); + } else { + gen_check_nanbox_h(out, in); + } + } else if (s->sew =3D=3D MO_32) { gen_check_nanbox_s(out, in); - break; - case 3: + } else if (s->sew =3D=3D MO_64) { tcg_gen_mov_i64(out, in); - break; - default: + } else { g_assert_not_reached(); } } diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 89d4f6fe67..d9df6a35ca 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -214,6 +214,14 @@ static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 = in) tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); } =20 +static void gen_check_nanbox_h_bf16(TCGv_i64 out, TCGv_i64 in) +{ + TCGv_i64 t_max =3D tcg_constant_i64(0xffffffffffff0000ull); + TCGv_i64 t_nan =3D tcg_constant_i64(0xffffffffffff7fc0ull); + + tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); +} + static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) { TCGv_i64 t_max =3D tcg_constant_i64(0xffffffff00000000ull); --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781212; cv=none; d=zohomail.com; s=zohoarc; b=QkdGg2kUY/WNUqBqbS7XolLKt1TIB9YqBeaOlwt9fgDFvC+Q4v3egcwoA7/2RJVEMskPApC3XOJvSCQtB9Jwff2YUO0DwxXrZrNApZdGP3BYwxLHlw7PUQ+Kkncc6sA9u2rf4K0fn9to92cpjJAtsTJDwEaA0kygIYbSIbkDcZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781212; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=rdvQkWw2uz2rql5RW4r1p5fi5ks6IEHCzWH9u7iWYVk=; b=JS+M9xK9hjZVkMDve6KGzz6myDzqCqEaCBWBzqm6BEfTc4bRZahFoKEmT1zVl2kQxSS5i+1i3bltT0yAl2DO8PXcScOtH7kNZJmElW5G2zwcKiWNvXCY1f0+X1bO3UMZIQG6tnSxQ+TTspAjLBylshNUUsZu+bsbGE56AuQQSfQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1772781212657478.05835397305907; Thu, 5 Mar 2026 23:13:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLc-0003GK-8V; Fri, 06 Mar 2026 02:11:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLT-0003F1-UP for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:36 -0500 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLP-0007lc-MY for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:35 -0500 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-826c49b7628so5633532b3a.0 for ; Thu, 05 Mar 2026 23:11:31 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781090; x=1773385890; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rdvQkWw2uz2rql5RW4r1p5fi5ks6IEHCzWH9u7iWYVk=; b=HdAJ5lRibdmUYizb9tKgyCw3EV5k0yGskSprQqXrkVIT2JO8QCrO+Jp7SuTIBnjADa 9/xy5xp1gK7bYyOkpxGKR0hFMCMll0zRpE1BoLf8DdzhhwMJdJ/mthicn8PtWYDu9wm2 e87pryosWkqdEox7IBjTMt3dkrRsF9XZZt80eTHZFivEtjygLLieIm63svQlnX+lKiGa pIA9Y8VVAGuIIoGNGo/Gd5jb8+CeXaiUPPP+OlnSs0ag+gIhMWq8P+/iSXZakeBfjqbb tdz1HhesavnwUaVDq0hi1UfVEySgIGOgPzeOQwnszYtrETwblF88epBIo9k+KeyQyKPl gsRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781090; x=1773385890; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=rdvQkWw2uz2rql5RW4r1p5fi5ks6IEHCzWH9u7iWYVk=; b=fagllqIvEufHH4ul05egItNWfdqxKEzki8+LZitdjvvEl8NthwVSxl7pwmM1/oafhK AklPc4E37jtCapkt4wZVBWUxWk1c1Gt/AC9CvSAibvwLRocJxzkT7WsceOCman7ed+BF 4HvOmcA12YuIOushFAxF6brg9bFNy22AS91wcTG4q+YH4BWARmLMYhUhTmMYKSHrrEaW SQyhCa0bhkYsbUEixZAU99JtR3pFggcQuOOCE9HjpMOBEnXJqK2x6VNwlu9/FrBR/bRV bIHjV/rpWzYOWfofgZ0NFzmC+2CFhWd9b77dEzJTTo+MoyufQsn+1Ev/2nyZhoOKI7SC KbUw== X-Gm-Message-State: AOJu0YxsQPs595eYXXpG7EWJUZqURdG4YWK24TEdy4owM/pcHyQiZIUs MmSu4okSwyLwQjh9PaQ0MSe3nB+70oxtnLVgbsbCUMEYfhSPKItl8Ni1ur581s/o5rVUCAUdFvW mtOgle1y9a7UH89txvZLyEh0kwpDK3gn/kO2W3zhAu4yaRyuVxKILMrDdz8Fbo7oSqzhKEyigss bMVuBswdxaQ1cdomWvRRberox4jWveKejMKSa3WZOuEWK6 X-Gm-Gg: ATEYQzzuE9jU3EUwbR3McIqgxeD69wA1MYXahjUURuRkwgNIIbbpiZwaXkZNPLi7/aa nlNDUyEWZdAl4k62MZXPx+J0b0wUh9f6zBON8uAnxWUMUbnlp5qCuZakNvpa5BYXcOeEpoZ0yc0 BSzmwxYgNC9fLDCny9LromzaVvNagiK2plCI+5XCWWpE1X5ISgIfMgqmpfQIcmVcoVmZx/A/VST Ecod0PxN4oNGcwadyrRiVe4n3cWfgQFCmd3iJxGG3p8jCXqdgW1Ky9Ld3bRB7RNhwdFa5Kca2LV 82+ZGr+IXQAY28MW8jMON97c+ilOm1NT1NV3b3uuv32qjXDDT3y1o+NgnvDoM63DeGCHo9Poqu3 8GD3aJ3B0scShEnrQwdD4zfnDGUUSg7KzCpkxj10r4dRgGz1BSgzpkyKm2IKh/HfMoCYnPYc9Wx lsXzrlAZ1aYAGOWxxaJCaphZq7KnPGKI6X2VybULJItrJRMTCvuLqRoomTD5HMv4G3JU+mUwF+J zUTGL4t38F1G3iSB+22fJh7QUY= X-Received: by 2002:a05:6a00:8d3:b0:829:7e11:d74a with SMTP id d2e1a72fcca58-829a30d1002mr926582b3a.66.1772781089605; Thu, 05 Mar 2026 23:11:29 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 8/9] target/riscv: rvv: Support Zvfbfa vector bf16 operations Date: Fri, 6 Mar 2026 15:11:03 +0800 Message-ID: <20260306071105.3328365-9-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781213069158500 Content-Type: text/plain; charset="utf-8" According to the Zvfbfa ISA spec v0.1, the following vector floating point instructions have different behaviors depend on the ALTFMT and VSEW fields of VTYPE CSR. When altfmt=3D1 and SEW=3D8, all vector floating-point instructions become reserved, except for the following, which are redefined to use the BF16 format for any operand that would otherwise have used the FP16 format: - vfwcvt.f.x[u].v, vfncvt.x[u].f.w, vfncvt.rtz.x[u].f.w When altfmt=3D1 and SEW=3D16, all vector floating-point instructions become reserved, except for the following, which are redefined to use the BF16 format for any operand that would otherwise have used the FP16 format: - vfadd.v[vf], vfsub.v[vf], vfmin.v[vf], vfmax.v[vf], vmfeq.v[vf], vmfle.v[vf], vmflt.v[vf], vmfne.v[vf], vmfgt.vf, vmfge.vf, vfmul.v[vf], vfrsub.vf, vfmadd.v[vf], vfnmadd.v[vf], vfmsub.v[vf], vfnmsub.v[vf], vfmacc.v[vf], vfnmacc.v[vf], vfmsac.v[vf], vfnmsac.v[vf], vfwadd.v[vf], vfwsub.v[vf], vfwadd.w[vf], vfwsub.w[vf], vfwmul.v[vf], vfwmacc.v[vf], vfwnmacc.v[vf], vfwmsac.v[vf], vfwnmsac.v[vf], vfwcvt.f.f.v, vfncvt.f.f.w, vfncvt.rod.f.f.w, vfrsqrt7.v, vfrec7.v, vfclass.v The following instructions marked with * have the same semantics regardless of altfmt. *- vfmv.f.s, vfwmaccbf16.v[vf] (only if Zvfbfwma is implemented) vfwcvtbf16.f.f.v (only if Zvfbfmin is implemented) vfncvtbf16.f.f.w (only if Zvfbfmin is implemented) The following instructions marked with ** differ only in that improperly NaN-boxed f-register operands must substitute the BF16 canonical NaN instead of the FP16 canonical NaN. **- vfsgnj.v[vf], vfsgnjn.v[vf], vfsgnjx.v[vf], vfslide1up.vf, vfslide1down.vf, vfmv.v.f, vfmerge.vfm, vfmv.s.f Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou --- target/riscv/helper.h | 60 ++ target/riscv/insn_trans/trans_rvv.c.inc | 970 +++++++++++++++--------- target/riscv/internals.h | 1 + target/riscv/vector_helper.c | 329 ++++++++ 4 files changed, 989 insertions(+), 371 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b785456ee0..eb0a488ba8 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -766,45 +766,60 @@ DEF_HELPER_6(vnclip_wx_b, void, ptr, ptr, tl, ptr, en= v, i32) DEF_HELPER_6(vnclip_wx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnclip_wx_w, void, ptr, ptr, tl, ptr, env, i32) =20 +DEF_HELPER_6(vfadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfrsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfrsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfrsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfrsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_6(vfwadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwadd_wv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwadd_wv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwadd_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwsub_wv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwsub_wv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwsub_wv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwadd_wf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwadd_wf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwsub_wf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwsub_wf_w, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_6(vfmul_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmul_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmul_vf_d, void, ptr, ptr, i64, ptr, env, i32) @@ -815,74 +830,98 @@ DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, e= nv, i32) DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_6(vfwmul_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmul_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_6(vfmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmacc_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsac_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmadd_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmadd_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmadd_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmadd_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfnmsub_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 DEF_HELPER_6(vfwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfwmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) =20 @@ -890,23 +929,29 @@ DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i3= 2) DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) =20 +DEF_HELPER_5(vfrsqrt7_v_h_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrsqrt7_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrsqrt7_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrsqrt7_v_d, void, ptr, ptr, ptr, env, i32) =20 +DEF_HELPER_5(vfrec7_v_h_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrec7_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrec7_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfrec7_v_d, void, ptr, ptr, ptr, env, i32) =20 +DEF_HELPER_6(vfmin_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmin_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmax_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmax_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmax_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmax_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfmin_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmin_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmin_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfmax_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32) @@ -930,37 +975,48 @@ DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, = env, i32) DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_6(vmfeq_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfeq_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfeq_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfeq_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmfne_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfne_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfne_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfne_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmflt_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmflt_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmflt_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmflt_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmfle_vv_h_bf16, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfle_vv_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfle_vv_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmfle_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vmfeq_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfeq_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfeq_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfeq_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vmfne_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfne_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfne_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfne_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vmflt_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmflt_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmflt_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmflt_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vmfle_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfle_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfle_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfle_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vmfgt_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfgt_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfgt_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfgt_vf_d, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vmfge_vf_h_bf16, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vmfge_vf_d, void, ptr, ptr, i64, ptr, env, i32) =20 +DEF_HELPER_5(vfclass_v_h_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) @@ -987,18 +1043,22 @@ DEF_HELPER_5(vfwcvt_xu_f_v_w, void, ptr, ptr, ptr, e= nv, i32) DEF_HELPER_5(vfwcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_xu_v_b_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfwcvt_f_x_v_b_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfwcvt_f_f_v_w, void, ptr, ptr, ptr, env, i32) =20 DEF_HELPER_5(vfncvt_xu_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_xu_f_w_b_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_xu_f_w_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_xu_f_w_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_x_f_w_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfncvt_x_f_w_b_bf16, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_x_f_w_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_x_f_w_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vfncvt_f_xu_w_h, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 03ae85796a..5b72926b3c 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -40,6 +40,9 @@ static bool require_rvf(DisasContext *s) =20 switch (s->sew) { case MO_16: + if (s->altfmt) { + return s->cfg_ptr->ext_zvfbfa; + } return s->cfg_ptr->ext_zvfh; case MO_32: return s->cfg_ptr->ext_zve32f; @@ -58,6 +61,9 @@ static bool require_rvfmin(DisasContext *s) =20 switch (s->sew) { case MO_16: + if (s->altfmt) { + return s->cfg_ptr->ext_zvfbfa; + } return s->cfg_ptr->ext_zvfhmin; case MO_32: return s->cfg_ptr->ext_zve32f; @@ -74,6 +80,9 @@ static bool require_scale_rvf(DisasContext *s) =20 switch (s->sew) { case MO_8: + if (s->altfmt) { + return s->cfg_ptr->ext_zvfbfa; + } return s->cfg_ptr->ext_zvfh; case MO_16: return s->cfg_ptr->ext_zve32f; @@ -2334,25 +2343,39 @@ static void do_nanbox(DisasContext *s, TCGv_i64 out= , TCGv_i64 in) } } =20 +/* + * Check altfmt & sew combinations when Zvfbfa extension is enabled. + */ +static bool vext_check_altfmt(DisasContext *s, int8_t valid_vsew) +{ + if (s->cfg_ptr->ext_zvfbfa) { + if (s->altfmt && (valid_vsew =3D=3D -1 || s->sew !=3D valid_vsew))= { + return false; + } + } + return true; +} + /* Vector Single-Width Floating-Point Add/Subtract Instructions */ =20 /* * If the current SEW does not correspond to a supported IEEE floating-poi= nt * type, an illegal instruction exception is raised. */ -static bool opfvv_check(DisasContext *s, arg_rmrr *a) +static bool opfvv_check(DisasContext *s, arg_rmrr *a, int8_t valid_bfa_vse= w) { return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); + vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 /* OPFVV without GVEC IR */ #define GEN_OPFVV_TRANS(NAME, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ { \ - if (CHECK(s, a)) { \ + if (CHECK(s, a, -1)) { \ uint32_t data =3D 0; \ static gen_helper_gvec_4_ptr * const fns[3] =3D { \ gen_helper_##NAME##_h, \ @@ -2378,8 +2401,41 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *= a) \ } \ return false; \ } -GEN_OPFVV_TRANS(vfadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsub_vv, opfvv_check) + +#define GEN_OPFVV_BFA_TRANS(NAME, CHECK, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_4_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1])); \ + tcg_gen_movi_tl(cpu_vstart, 0); \ + finalize_rvv_inst(s); \ + \ + return true; \ + } \ + return false; \ +} + +GEN_OPFVV_BFA_TRANS(vfadd_vv, opfvv_check, vfadd_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfsub_vv, opfvv_check, vfsub_vv_h_bf16) =20 typedef void gen_helper_opfvf(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_ptr, TCGv_env, TCGv_i32); @@ -2415,244 +2471,316 @@ static bool opfvf_trans(uint32_t vd, uint32_t rs1= , uint32_t vs2, * If the current SEW does not correspond to a supported IEEE floating-poi= nt * type, an illegal instruction exception is raised */ -static bool opfvf_check(DisasContext *s, arg_rmrr *a) +static bool opfvf_check(DisasContext *s, arg_rmrr *a, int8_t valid_bfa_vse= w) { return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_ss(s, a->rd, a->rs2, a->vm); + vext_check_ss(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 /* OPFVF without GVEC IR */ -#define GEN_OPFVF_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_opfvf *const fns[3] =3D { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, \ - s->cfg_vta_all_1s); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFVF_TRANS(vfadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsub_vf, opfvf_check) -GEN_OPFVF_TRANS(vfrsub_vf, opfvf_check) +#define GEN_OPFVF_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, -1)) { \ + uint32_t data =3D 0; \ + static gen_helper_opfvf *const fns[3] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, \ + s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + fns[s->sew - 1], s); \ + } \ + return false; \ +} + +#define GEN_OPFVF_BFA_TRANS(NAME, CHECK, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_opfvf *const fns[3] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VTA_ALL_1S, \ + s->cfg_vta_all_1s); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1]), \ + s); \ + } \ + return false; \ +} + +GEN_OPFVF_BFA_TRANS(vfadd_vf, opfvf_check, vfadd_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfsub_vf, opfvf_check, vfsub_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfrsub_vf, opfvf_check, vfrsub_vf_h_bf16) =20 /* Vector Widening Floating-Point Add/Subtract Instructions */ -static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a) +static bool opfvv_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && - vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm); + vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a) +static bool opfvv_overwrite_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { - return require_rvv(s) && - require_rvf(s) && - require_scale_rvf(s) && - vext_check_isa_ill(s) && - vext_check_dss(s, a->rd, a->rs1, a->rs2, a->vm) && + return opfvv_widen_check(s, a, valid_bfa_vsew) && vext_check_input_eew(s, a->rd, s->sew + 1, a->rs1, s->sew, a->v= m) && vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->v= m); } =20 /* OPFVV with WIDEN */ -#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_4_ptr * const fns[2] =3D { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew - 1]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ -} - -GEN_OPFVV_WIDEN_TRANS(vfwadd_vv, opfvv_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwsub_vv, opfvv_widen_check) - -static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a) +#define GEN_OPFVV_WIDEN_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, -1)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_4_ptr * const fns[2] =3D { \ + gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + fns[s->sew - 1]); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ +} + +#define GEN_OPFVV_WIDEN_BFA_TRANS(NAME, CHECK, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_4_ptr * const fns[2] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFVV_WIDEN_BFA_TRANS(vfwadd_vv, opfvv_widen_check, vfwadd_vv_h_bf16) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwsub_vv, opfvv_widen_check, vfwsub_vv_h_bf16) + +static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && - vext_check_ds(s, a->rd, a->rs2, a->vm); + vext_check_ds(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a) +static bool opfvf_overwrite_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { - return require_rvv(s) && - require_rvf(s) && - require_scale_rvf(s) && - vext_check_isa_ill(s) && - vext_check_ds(s, a->rd, a->rs2, a->vm) && + return opfvf_widen_check(s, a, valid_bfa_vsew) && vext_check_input_eew(s, a->rd, s->sew + 1, a->rs2, s->sew, a->v= m); } =20 /* OPFVF with WIDEN */ -#define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_opfvf *const fns[2] =3D { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check) - -static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) +#define GEN_OPFVF_WIDEN_BFA_TRANS(NAME, CHECK, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_opfvf *const fns[2] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1]), \ + s); \ + } \ + return false; \ +} + +GEN_OPFVF_WIDEN_BFA_TRANS(vfwadd_vf, opfvf_widen_check, vfwadd_vf_h_bf16) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwsub_vf, opfvf_widen_check, vfwsub_vf_h_bf16) + +static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && - vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm); + vext_check_dds(s, a->rd, a->rs1, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 /* WIDEN OPFVV with WIDEN */ -#define GEN_OPFWV_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opfwv_widen_check(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_4_ptr * const fns[2] =3D { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs1), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew - 1]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ +#define GEN_OPFWV_WIDEN_BFA_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opfwv_widen_check(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_4_ptr * const fns[2] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \ + fns[s->sew - 1])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ } =20 -GEN_OPFWV_WIDEN_TRANS(vfwadd_wv) -GEN_OPFWV_WIDEN_TRANS(vfwsub_wv) +GEN_OPFWV_WIDEN_BFA_TRANS(vfwadd_wv) +GEN_OPFWV_WIDEN_BFA_TRANS(vfwsub_wv) =20 -static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a) +static bool opfwf_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && - vext_check_dd(s, a->rd, a->rs2, a->vm); + vext_check_dd(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 /* WIDEN OPFVF with WIDEN */ -#define GEN_OPFWF_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ -{ \ - if (opfwf_widen_check(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_opfvf *const fns[2] =3D { \ - gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ - fns[s->sew - 1], s); \ - } \ - return false; \ -} - -GEN_OPFWF_WIDEN_TRANS(vfwadd_wf) -GEN_OPFWF_WIDEN_TRANS(vfwsub_wf) +#define GEN_OPFWF_WIDEN_BFA_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (opfwf_widen_check(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_opfvf *const fns[2] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + return opfvf_trans(a->rd, a->rs1, a->rs2, data, \ + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \ + fns[s->sew - 1]), \ + s); \ + } \ + return false; \ +} + +GEN_OPFWF_WIDEN_BFA_TRANS(vfwadd_wf) +GEN_OPFWF_WIDEN_BFA_TRANS(vfwsub_wf) =20 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */ -GEN_OPFVV_TRANS(vfmul_vv, opfvv_check) +GEN_OPFVV_BFA_TRANS(vfmul_vv, opfvv_check, vfmul_vv_h_bf16) GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmul_vf, opfvf_check) +GEN_OPFVF_BFA_TRANS(vfmul_vf, opfvf_check, vfmul_vf_h_bf16) GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check) GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check) =20 /* Vector Widening Floating-Point Multiply */ -GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmul_vv, opfvv_widen_check, vfwmul_vv_h_bf16) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmul_vf, opfvf_widen_check, vfwmul_vf_h_bf16) =20 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ -GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmacc_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmsac_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmsac_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmadd_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmsub_vv, opfvv_check) -GEN_OPFVV_TRANS(vfnmsub_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmacc_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmacc_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmsac_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmsac_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check) -GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check) +GEN_OPFVV_BFA_TRANS(vfmacc_vv, opfvv_check, vfmacc_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfnmacc_vv, opfvv_check, vfnmacc_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfmsac_vv, opfvv_check, vfmsac_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfnmsac_vv, opfvv_check, vfnmsac_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfmadd_vv, opfvv_check, vfmadd_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfnmadd_vv, opfvv_check, vfnmadd_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfmsub_vv, opfvv_check, vfmsub_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfnmsub_vv, opfvv_check, vfnmsub_vv_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmacc_vf, opfvf_check, vfmacc_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfnmacc_vf, opfvf_check, vfnmacc_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmsac_vf, opfvf_check, vfmsac_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfnmsac_vf, opfvf_check, vfnmsac_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmadd_vf, opfvf_check, vfmadd_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfnmadd_vf, opfvf_check, vfnmadd_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmsub_vf, opfvf_check, vfmsub_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfnmsub_vf, opfvf_check, vfnmsub_vf_h_bf16) =20 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */ -GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check) -GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check) -GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmacc_vv, opfvv_overwrite_widen_check, + vfwmaccbf16_vv) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwnmacc_vv, opfvv_overwrite_widen_check, + vfwnmacc_vv_h_bf16) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwmsac_vv, opfvv_overwrite_widen_check, + vfwmsac_vv_h_bf16) +GEN_OPFVV_WIDEN_BFA_TRANS(vfwnmsac_vv, opfvv_overwrite_widen_check, + vfwnmsac_vv_h_bf16) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmacc_vf, opfvf_overwrite_widen_check, + vfwmaccbf16_vf) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwnmacc_vf, opfvf_overwrite_widen_check, + vfwnmacc_vf_h_bf16) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwmsac_vf, opfvf_overwrite_widen_check, + vfwmsac_vf_h_bf16) +GEN_OPFVF_WIDEN_BFA_TRANS(vfwnmsac_vf, opfvf_overwrite_widen_check, + vfwnmsac_vf_h_bf16) =20 /* Vector Floating-Point Square-Root Instruction */ =20 @@ -2660,21 +2788,23 @@ GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_overwrite_= widen_check) * If the current SEW does not correspond to a supported IEEE floating-poi= nt * type, an illegal instruction exception is raised */ -static bool opfv_check(DisasContext *s, arg_rmr *a) +static bool opfv_check(DisasContext *s, arg_rmr *a, int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && /* OPFV instructions ignore vs1 check */ - vext_check_ss(s, a->rd, a->rs2, a->vm); + vext_check_ss(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 static bool do_opfv(DisasContext *s, arg_rmr *a, gen_helper_gvec_3_ptr *fn, - bool (*checkfn)(DisasContext *, arg_rmr *), - int rm) + bool (*checkfn)(DisasContext *, arg_rmr *, int8_t), + int rm, + int8_t valid_bfa_vsew) { - if (checkfn(s, a)) { + if (checkfn(s, a, valid_bfa_vsew)) { uint32_t data =3D 0; gen_set_rm_chkfrm(s, rm); =20 @@ -2692,76 +2822,95 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, return false; } =20 -#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - static gen_helper_gvec_3_ptr * const fns[3] =3D { \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - gen_helper_##NAME##_d \ - }; \ - return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM); \ +#define GEN_OPFV_TRANS(NAME, CHECK, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], CHECK, FRM, -1); \ +} + +#define GEN_OPFV_BFA_TRANS(NAME, CHECK, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d \ + }; \ + return do_opfv(s, a, \ + (s->altfmt ? gen_helper_##NAME##_h_bf16 : \ + fns[s->sew - 1]), \ + CHECK, FRM, MO_16); \ } =20 GEN_OPFV_TRANS(vfsqrt_v, opfv_check, RISCV_FRM_DYN) -GEN_OPFV_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) -GEN_OPFV_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_BFA_TRANS(vfrsqrt7_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_BFA_TRANS(vfrec7_v, opfv_check, RISCV_FRM_DYN) =20 /* Vector Floating-Point MIN/MAX Instructions */ -GEN_OPFVV_TRANS(vfmin_vv, opfvv_check) -GEN_OPFVV_TRANS(vfmax_vv, opfvv_check) -GEN_OPFVF_TRANS(vfmin_vf, opfvf_check) -GEN_OPFVF_TRANS(vfmax_vf, opfvf_check) +GEN_OPFVV_BFA_TRANS(vfmin_vv, opfvv_check, vfmin_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vfmax_vv, opfvv_check, vfmax_vv_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmin_vf, opfvf_check, vfmin_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vfmax_vf, opfvf_check, vfmax_vf_h_bf16) =20 /* Vector Floating-Point Sign-Injection Instructions */ -GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check) -GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check) -GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check) -GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check) +GEN_OPFVV_BFA_TRANS(vfsgnj_vv, opfvv_check, vfsgnj_vv_h) +GEN_OPFVV_BFA_TRANS(vfsgnjn_vv, opfvv_check, vfsgnjn_vv_h) +GEN_OPFVV_BFA_TRANS(vfsgnjx_vv, opfvv_check, vfsgnjx_vv_h) +GEN_OPFVF_BFA_TRANS(vfsgnj_vf, opfvf_check, vfsgnj_vf_h) +GEN_OPFVF_BFA_TRANS(vfsgnjn_vf, opfvf_check, vfsgnjn_vf_h) +GEN_OPFVF_BFA_TRANS(vfsgnjx_vf, opfvf_check, vfsgnjx_vf_h) =20 /* Vector Floating-Point Compare Instructions */ -static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a) +static bool opfvv_cmp_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_mss(s, a->rd, a->rs1, a->rs2); + vext_check_mss(s, a->rd, a->rs1, a->rs2) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -GEN_OPFVV_TRANS(vmfeq_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmfne_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmflt_vv, opfvv_cmp_check) -GEN_OPFVV_TRANS(vmfle_vv, opfvv_cmp_check) +GEN_OPFVV_BFA_TRANS(vmfeq_vv, opfvv_cmp_check, vmfeq_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vmfne_vv, opfvv_cmp_check, vmfne_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vmflt_vv, opfvv_cmp_check, vmflt_vv_h_bf16) +GEN_OPFVV_BFA_TRANS(vmfle_vv, opfvv_cmp_check, vmfle_vv_h_bf16) =20 -static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a) +static bool opfvf_cmp_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - vext_check_ms(s, a->rd, a->rs2); + vext_check_ms(s, a->rd, a->rs2) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -GEN_OPFVF_TRANS(vmfeq_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfne_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmflt_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check) -GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check) +GEN_OPFVF_BFA_TRANS(vmfeq_vf, opfvf_cmp_check, vmfeq_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vmfne_vf, opfvf_cmp_check, vmfne_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vmflt_vf, opfvf_cmp_check, vmflt_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vmfle_vf, opfvf_cmp_check, vmfle_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vmfgt_vf, opfvf_cmp_check, vmfgt_vf_h_bf16) +GEN_OPFVF_BFA_TRANS(vmfge_vf, opfvf_cmp_check, vmfge_vf_h_bf16) =20 /* Vector Floating-Point Classify Instruction */ -GEN_OPFV_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN) +GEN_OPFV_BFA_TRANS(vfclass_v, opfv_check, RISCV_FRM_DYN) =20 /* Vector Floating-Point Merge Instruction */ -GEN_OPFVF_TRANS(vfmerge_vfm, opfvf_check) +GEN_OPFVF_BFA_TRANS(vfmerge_vfm, opfvf_check, vfmerge_vfm_h) =20 static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) { if (require_rvv(s) && require_rvf(s) && vext_check_isa_ill(s) && - require_align(a->rd, s->lmul)) { + require_align(a->rd, s->lmul) && + vext_check_altfmt(s, MO_16)) { gen_set_rm(s, RISCV_FRM_DYN); =20 TCGv_i64 t1; @@ -2782,7 +2931,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_= v_f *a) static gen_helper_vmv_vx * const fns[3] =3D { gen_helper_vmv_v_x_h, gen_helper_vmv_v_x_w, - gen_helper_vmv_v_x_d, + gen_helper_vmv_v_x_d }; =20 t1 =3D tcg_temp_new_i64(); @@ -2803,15 +2952,15 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfm= v_v_f *a) } =20 /* Single-Width Floating-Point/Integer Type-Convert Instructions */ -#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - static gen_helper_gvec_3_ptr * const fns[3] =3D { \ - gen_helper_##HELPER##_h, \ - gen_helper_##HELPER##_w, \ - gen_helper_##HELPER##_d \ - }; \ - return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM); \ +#define GEN_OPFV_CVT_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + gen_helper_##HELPER##_d \ + }; \ + return do_opfv(s, a, fns[s->sew - 1], opfv_check, FRM, -1); \ } =20 GEN_OPFV_CVT_TRANS(vfcvt_xu_f_v, vfcvt_xu_f_v, RISCV_FRM_DYN) @@ -2835,95 +2984,129 @@ static bool opfv_widen_check(DisasContext *s, arg_= rmr *a) vext_check_ds(s, a->rd, a->rs2, a->vm); } =20 -static bool opxfv_widen_check(DisasContext *s, arg_rmr *a) +static bool opxfv_widen_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return opfv_widen_check(s, a) && - require_rvf(s); + require_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool opffv_widen_check(DisasContext *s, arg_rmr *a) +static bool opffv_widen_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return opfv_widen_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s); -} - -#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_3_ptr * const fns[2] =3D { \ - gen_helper_##HELPER##_h, \ - gen_helper_##HELPER##_w, \ - }; \ - gen_set_rm_chkfrm(s, FRM); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew - 1]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ + require_scale_rvfmin(s) && + vext_check_altfmt(s, valid_bfa_vsew); +} + +#define GEN_OPFV_WIDEN_TRANS(NAME, CHECK, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (CHECK(s, a, -1)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[2] =3D { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + gen_set_rm_chkfrm(s, FRM); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + fns[s->sew - 1]); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ +} + +#define GEN_OPFV_WIDEN_BFA_TRANS(NAME, CHECK, HELPER, FRM, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[2] =3D { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + gen_set_rm_chkfrm(s, FRM); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ } =20 GEN_OPFV_WIDEN_TRANS(vfwcvt_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v, RISCV_FRM_DYN) GEN_OPFV_WIDEN_TRANS(vfwcvt_x_f_v, opxfv_widen_check, vfwcvt_x_f_v, RISCV_FRM_DYN) -GEN_OPFV_WIDEN_TRANS(vfwcvt_f_f_v, opffv_widen_check, vfwcvt_f_f_v, - RISCV_FRM_DYN) +GEN_OPFV_WIDEN_BFA_TRANS(vfwcvt_f_f_v, opffv_widen_check, vfwcvt_f_f_v, + RISCV_FRM_DYN, vfwcvtbf16_f_f_v) /* Reuse the helper functions from vfwcvt.xu.f.v and vfwcvt.x.f.v */ GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_xu_f_v, opxfv_widen_check, vfwcvt_xu_f_v, RISCV_FRM_RTZ) GEN_OPFV_WIDEN_TRANS(vfwcvt_rtz_x_f_v, opxfv_widen_check, vfwcvt_x_f_v, RISCV_FRM_RTZ) =20 -static bool opfxv_widen_check(DisasContext *s, arg_rmr *a) +static bool opfxv_widen_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && /* OPFV widening instructions ignore vs1 check */ - vext_check_ds(s, a->rd, a->rs2, a->vm); + vext_check_ds(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -#define GEN_OPFXV_WIDEN_TRANS(NAME) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (opfxv_widen_check(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_3_ptr * const fns[3] =3D { \ - gen_helper_##NAME##_b, \ - gen_helper_##NAME##_h, \ - gen_helper_##NAME##_w, \ - }; \ - gen_set_rm(s, RISCV_FRM_DYN); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ +#define GEN_OPFXV_WIDEN_BFA_TRANS(NAME) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opfxv_widen_check(s, a, MO_8)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w \ + }; \ + gen_set_rm(s, RISCV_FRM_DYN); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##NAME##_b_bf16 : \ + fns[s->sew])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ } =20 -GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_xu_v) -GEN_OPFXV_WIDEN_TRANS(vfwcvt_f_x_v) +GEN_OPFXV_WIDEN_BFA_TRANS(vfwcvt_f_xu_v) +GEN_OPFXV_WIDEN_BFA_TRANS(vfwcvt_f_x_v) =20 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ =20 @@ -2939,104 +3122,140 @@ static bool opfv_narrow_check(DisasContext *s, ar= g_rmr *a) vext_check_sd(s, a->rd, a->rs2, a->vm); } =20 -static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a) +static bool opfxv_narrow_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return opfv_narrow_check(s, a) && require_rvf(s) && - (s->sew !=3D MO_64); + (s->sew !=3D MO_64) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) +static bool opffv_narrow_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return opfv_narrow_check(s, a) && require_rvfmin(s) && - require_scale_rvfmin(s); + require_scale_rvfmin(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a) +static bool opffv_rod_narrow_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return opfv_narrow_check(s, a) && require_rvf(s) && - require_scale_rvf(s); -} - -#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (CHECK(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_3_ptr * const fns[2] =3D { \ - gen_helper_##HELPER##_h, \ - gen_helper_##HELPER##_w, \ - }; \ - gen_set_rm_chkfrm(s, FRM); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew - 1]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ + require_scale_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); +} + +#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (CHECK(s, a, -1)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[2] =3D { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + gen_set_rm_chkfrm(s, FRM); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + fns[s->sew - 1]); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ +} + +#define GEN_OPFV_NARROW_BFA_TRANS(NAME, CHECK, HELPER, FRM, BFA_HELPER) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (CHECK(s, a, MO_16)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[2] =3D { \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w, \ + }; \ + gen_set_rm_chkfrm(s, FRM); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##BFA_HELPER : \ + fns[s->sew - 1])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ } =20 GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, opfxv_narrow_check, vfncvt_f_xu_w, RISCV_FRM_DYN) GEN_OPFV_NARROW_TRANS(vfncvt_f_x_w, opfxv_narrow_check, vfncvt_f_x_w, RISCV_FRM_DYN) -GEN_OPFV_NARROW_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, - RISCV_FRM_DYN) +GEN_OPFV_NARROW_BFA_TRANS(vfncvt_f_f_w, opffv_narrow_check, vfncvt_f_f_w, + RISCV_FRM_DYN, vfncvtbf16_f_f_w) /* Reuse the helper function from vfncvt.f.f.w */ -GEN_OPFV_NARROW_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, vfncvt_f_f= _w, - RISCV_FRM_ROD) +GEN_OPFV_NARROW_BFA_TRANS(vfncvt_rod_f_f_w, opffv_rod_narrow_check, + vfncvt_f_f_w, RISCV_FRM_ROD, vfncvtbf16_f_f_w) =20 -static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) +static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a, + int8_t valid_bfa_vsew) { return require_rvv(s) && require_scale_rvf(s) && vext_check_isa_ill(s) && /* OPFV narrowing instructions ignore vs1 check */ - vext_check_sd(s, a->rd, a->rs2, a->vm); + vext_check_sd(s, a->rd, a->rs2, a->vm) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -#define GEN_OPXFV_NARROW_TRANS(NAME, HELPER, FRM) \ -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ -{ \ - if (opxfv_narrow_check(s, a)) { \ - uint32_t data =3D 0; \ - static gen_helper_gvec_3_ptr * const fns[3] =3D { \ - gen_helper_##HELPER##_b, \ - gen_helper_##HELPER##_h, \ - gen_helper_##HELPER##_w, \ - }; \ - gen_set_rm_chkfrm(s, FRM); \ - \ - data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ - data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ - data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ - data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ - vreg_ofs(s, a->rs2), tcg_env, \ - s->cfg_ptr->vlenb, \ - s->cfg_ptr->vlenb, data, \ - fns[s->sew]); \ - finalize_rvv_inst(s); \ - return true; \ - } \ - return false; \ +#define GEN_OPXFV_NARROW_BFA_TRANS(NAME, HELPER, FRM) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + if (opxfv_narrow_check(s, a, MO_8)) { \ + uint32_t data =3D 0; \ + static gen_helper_gvec_3_ptr * const fns[3] =3D { \ + gen_helper_##HELPER##_b, \ + gen_helper_##HELPER##_h, \ + gen_helper_##HELPER##_w \ + }; \ + gen_set_rm_chkfrm(s, FRM); \ + \ + data =3D FIELD_DP32(data, VDATA, VM, a->vm); \ + data =3D FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data =3D FIELD_DP32(data, VDATA, VTA, s->vta); \ + data =3D FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_env, \ + s->cfg_ptr->vlenb, \ + s->cfg_ptr->vlenb, data, \ + (s->altfmt ? gen_helper_##HELPER##_b_bf16 : \ + fns[s->sew])); \ + finalize_rvv_inst(s); \ + return true; \ + } \ + return false; \ } =20 -GEN_OPXFV_NARROW_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN) -GEN_OPXFV_NARROW_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN) +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_DYN) +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_x_f_w, vfncvt_x_f_w, RISCV_FRM_DYN) /* Reuse the helper functions from vfncvt.xu.f.w and vfncvt.x.f.w */ -GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ) -GEN_OPXFV_NARROW_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ) +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_rtz_xu_f_w, vfncvt_xu_f_w, RISCV_FRM_RTZ) +GEN_OPXFV_NARROW_BFA_TRANS(vfncvt_rtz_x_f_w, vfncvt_x_f_w, RISCV_FRM_RTZ) =20 /* *** Vector Reduction Operations @@ -3069,10 +3288,12 @@ GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_widen_= check) GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_widen_check) =20 /* Vector Single-Width Floating-Point Reduction Instructions */ -static bool freduction_check(DisasContext *s, arg_rmrr *a) +static bool freduction_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return reduction_check(s, a) && - require_rvf(s); + require_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 GEN_OPFVV_TRANS(vfredusum_vs, freduction_check) @@ -3081,11 +3302,13 @@ GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) =20 /* Vector Widening Floating-Point Reduction Instructions */ -static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) +static bool freduction_widen_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return reduction_widen_check(s, a) && require_rvf(s) && - require_scale_rvf(s); + require_scale_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) @@ -3500,7 +3723,8 @@ static bool trans_vfmv_s_f(DisasContext *s, arg_vfmv_= s_f *a) { if (require_rvv(s) && require_rvf(s) && - vext_check_isa_ill(s)) { + vext_check_isa_ill(s) && + vext_check_altfmt(s, MO_16)) { gen_set_rm(s, RISCV_FRM_DYN); =20 /* The instructions ignore LMUL and vector register group. */ @@ -3594,20 +3818,24 @@ GEN_OPIVX_VSLIDE1_TRANS(vslide1up_vx, slideup_check) GEN_OPIVX_VSLIDE1_TRANS(vslide1down_vx, slidedown_check) =20 /* Vector Floating-Point Slide Instructions */ -static bool fslideup_check(DisasContext *s, arg_rmrr *a) +static bool fslideup_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return slideup_check(s, a) && - require_rvf(s); + require_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -static bool fslidedown_check(DisasContext *s, arg_rmrr *a) +static bool fslidedown_check(DisasContext *s, arg_rmrr *a, + int8_t valid_bfa_vsew) { return slidedown_check(s, a) && - require_rvf(s); + require_rvf(s) && + vext_check_altfmt(s, valid_bfa_vsew); } =20 -GEN_OPFVF_TRANS(vfslide1up_vf, fslideup_check) -GEN_OPFVF_TRANS(vfslide1down_vf, fslidedown_check) +GEN_OPFVF_BFA_TRANS(vfslide1up_vf, fslideup_check, vfslide1up_vf_h) +GEN_OPFVF_BFA_TRANS(vfslide1down_vf, fslidedown_check, vfslide1down_vf_h) =20 /* Vector Register Gather Instruction */ static bool vrgather_vv_check(DisasContext *s, arg_rmrr *a) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 35b923c4bf..db7d7dce63 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -72,6 +72,7 @@ FIELD(VDATA, NF, 7, 4) FIELD(VDATA, WD, 7, 1) =20 /* float point classify helpers */ +target_ulong fclass_h_bf16(uint64_t frs1); target_ulong fclass_h(uint64_t frs1); target_ulong fclass_s(uint64_t frs1); target_ulong fclass_d(uint64_t frs1); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index b7105627ed..f75177b0fc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3177,9 +3177,11 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, = \ total_elems * ESZ); \ } =20 +RVVCALL(OPFVV2, vfadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_add) RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add) RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add) +GEN_VEXT_VV_ENV(vfadd_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfadd_vv_h, 2) GEN_VEXT_VV_ENV(vfadd_vv_w, 4) GEN_VEXT_VV_ENV(vfadd_vv_d, 8) @@ -3222,26 +3224,37 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = \ total_elems * ESZ); \ } =20 +RVVCALL(OPFVF2, vfadd_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_add) RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add) RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add) +GEN_VEXT_VF(vfadd_vf_h_bf16, 2) GEN_VEXT_VF(vfadd_vf_h, 2) GEN_VEXT_VF(vfadd_vf_w, 4) GEN_VEXT_VF(vfadd_vf_d, 8) =20 +RVVCALL(OPFVV2, vfsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_sub) RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub) RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub) RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub) +GEN_VEXT_VV_ENV(vfsub_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfsub_vv_h, 2) GEN_VEXT_VV_ENV(vfsub_vv_w, 4) GEN_VEXT_VV_ENV(vfsub_vv_d, 8) +RVVCALL(OPFVF2, vfsub_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_sub) RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub) RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub) RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub) +GEN_VEXT_VF(vfsub_vf_h_bf16, 2) GEN_VEXT_VF(vfsub_vf_h, 2) GEN_VEXT_VF(vfsub_vf_w, 4) GEN_VEXT_VF(vfsub_vf_d, 8) =20 +static uint16_t bfloat16_rsub(uint16_t a, uint16_t b, float_status * s) +{ + return bfloat16_sub(b, a, s); +} + static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) { return float16_sub(b, a, s); @@ -3257,14 +3270,22 @@ static uint64_t float64_rsub(uint64_t a, uint64_t b= , float_status *s) return float64_sub(b, a, s); } =20 +RVVCALL(OPFVF2, vfrsub_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_rsub) RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub) RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub) RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub) +GEN_VEXT_VF(vfrsub_vf_h_bf16, 2) GEN_VEXT_VF(vfrsub_vf_h, 2) GEN_VEXT_VF(vfrsub_vf_w, 4) GEN_VEXT_VF(vfrsub_vf_d, 8) =20 /* Vector Widening Floating-Point Add/Subtract Instructions */ +static uint32_t vfwadd16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + return float32_add(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), s); +} + static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) { return float32_add(float16_to_float32(a, true, s), @@ -3278,15 +3299,25 @@ static uint64_t vfwadd32(uint32_t a, uint32_t b, fl= oat_status *s) =20 } =20 +RVVCALL(OPFVV2, vfwadd_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwadd16_bf16) RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16) RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32) +GEN_VEXT_VV_ENV(vfwadd_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwadd_vv_h, 4) GEN_VEXT_VV_ENV(vfwadd_vv_w, 8) +RVVCALL(OPFVF2, vfwadd_vf_h_bf16, WOP_UUU_H, H4, H2, vfwadd16_bf16) RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16) RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32) +GEN_VEXT_VF(vfwadd_vf_h_bf16, 4) GEN_VEXT_VF(vfwadd_vf_h, 4) GEN_VEXT_VF(vfwadd_vf_w, 8) =20 +static uint32_t vfwsub16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + return float32_sub(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), s); +} + static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) { return float32_sub(float16_to_float32(a, true, s), @@ -3300,15 +3331,24 @@ static uint64_t vfwsub32(uint32_t a, uint32_t b, fl= oat_status *s) =20 } =20 +RVVCALL(OPFVV2, vfwsub_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwsub16_bf16) RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16) RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32) +GEN_VEXT_VV_ENV(vfwsub_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwsub_vv_h, 4) GEN_VEXT_VV_ENV(vfwsub_vv_w, 8) +RVVCALL(OPFVF2, vfwsub_vf_h_bf16, WOP_UUU_H, H4, H2, vfwsub16_bf16) RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16) RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32) +GEN_VEXT_VF(vfwsub_vf_h_bf16, 4) GEN_VEXT_VF(vfwsub_vf_h, 4) GEN_VEXT_VF(vfwsub_vf_w, 8) =20 +static uint32_t vfwaddw16_bf16(uint32_t a, uint16_t b, float_status *s) +{ + return float32_add(a, bfloat16_to_float32(b, s), s); +} + static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s) { return float32_add(a, float16_to_float32(b, true, s), s); @@ -3319,15 +3359,24 @@ static uint64_t vfwaddw32(uint64_t a, uint32_t b, f= loat_status *s) return float64_add(a, float32_to_float64(b, s), s); } =20 +RVVCALL(OPFVV2, vfwadd_wv_h_bf16, WOP_WUUU_H, H4, H2, H2, vfwaddw16_bf16) RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16) RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32) +GEN_VEXT_VV_ENV(vfwadd_wv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwadd_wv_h, 4) GEN_VEXT_VV_ENV(vfwadd_wv_w, 8) +RVVCALL(OPFVF2, vfwadd_wf_h_bf16, WOP_WUUU_H, H4, H2, vfwaddw16_bf16) RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16) RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32) +GEN_VEXT_VF(vfwadd_wf_h_bf16, 4) GEN_VEXT_VF(vfwadd_wf_h, 4) GEN_VEXT_VF(vfwadd_wf_w, 8) =20 +static uint32_t vfwsubw16_bf16(uint32_t a, uint16_t b, float_status *s) +{ + return float32_sub(a, bfloat16_to_float32(b, s), s); +} + static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s) { return float32_sub(a, float16_to_float32(b, true, s), s); @@ -3338,25 +3387,33 @@ static uint64_t vfwsubw32(uint64_t a, uint32_t b, f= loat_status *s) return float64_sub(a, float32_to_float64(b, s), s); } =20 +RVVCALL(OPFVV2, vfwsub_wv_h_bf16, WOP_WUUU_H, H4, H2, H2, vfwsubw16_bf16) RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16) RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32) +GEN_VEXT_VV_ENV(vfwsub_wv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwsub_wv_h, 4) GEN_VEXT_VV_ENV(vfwsub_wv_w, 8) +RVVCALL(OPFVF2, vfwsub_wf_h_bf16, WOP_WUUU_H, H4, H2, vfwsubw16_bf16) RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) +GEN_VEXT_VF(vfwsub_wf_h_bf16, 4) GEN_VEXT_VF(vfwsub_wf_h, 4) GEN_VEXT_VF(vfwsub_wf_w, 8) =20 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */ +RVVCALL(OPFVV2, vfmul_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_mul) RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) +GEN_VEXT_VV_ENV(vfmul_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmul_vv_h, 2) GEN_VEXT_VV_ENV(vfmul_vv_w, 4) GEN_VEXT_VV_ENV(vfmul_vv_d, 8) +RVVCALL(OPFVF2, vfmul_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_mul) RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) +GEN_VEXT_VF(vfmul_vf_h_bf16, 2) GEN_VEXT_VF(vfmul_vf_h, 2) GEN_VEXT_VF(vfmul_vf_w, 4) GEN_VEXT_VF(vfmul_vf_d, 8) @@ -3397,6 +3454,12 @@ GEN_VEXT_VF(vfrdiv_vf_w, 4) GEN_VEXT_VF(vfrdiv_vf_d, 8) =20 /* Vector Widening Floating-Point Multiply */ +static uint32_t vfwmul16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + return float32_mul(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), s); +} + static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) { return float32_mul(float16_to_float32(a, true, s), @@ -3409,12 +3472,17 @@ static uint64_t vfwmul32(uint32_t a, uint32_t b, fl= oat_status *s) float32_to_float64(b, s), s); =20 } + +RVVCALL(OPFVV2, vfwmul_vv_h_bf16, WOP_UUU_H, H4, H2, H2, vfwmul16_bf16) RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32) +GEN_VEXT_VV_ENV(vfwmul_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwmul_vv_h, 4) GEN_VEXT_VV_ENV(vfwmul_vv_w, 8) +RVVCALL(OPFVF2, vfwmul_vf_h_bf16, WOP_UUU_H, H4, H2, vfwmul16_bf16) RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16) RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32) +GEN_VEXT_VF(vfwmul_vf_h_bf16, 4) GEN_VEXT_VF(vfwmul_vf_h, 4) GEN_VEXT_VF(vfwmul_vf_w, 8) =20 @@ -3429,6 +3497,12 @@ static void do_##NAME(void *vd, void *vs1, void *vs2= , int i, \ *((TD *)vd + HD(i)) =3D OP(s2, s1, d, &env->fp_status); \ } =20 +static uint16_t fmacc16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(a, b, d, 0, s); +} + static uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *= s) { return float16_muladd(a, b, d, 0, s); @@ -3444,9 +3518,11 @@ static uint64_t fmacc64(uint64_t a, uint64_t b, uint= 64_t d, float_status *s) return float64_muladd(a, b, d, 0, s); } =20 +RVVCALL(OPFVV3, vfmacc_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmacc16_bf16) RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16) RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32) RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64) +GEN_VEXT_VV_ENV(vfmacc_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmacc_vv_h, 2) GEN_VEXT_VV_ENV(vfmacc_vv_w, 4) GEN_VEXT_VV_ENV(vfmacc_vv_d, 8) @@ -3460,13 +3536,22 @@ static void do_##NAME(void *vd, uint64_t s1, void *= vs2, int i, \ *((TD *)vd + HD(i)) =3D OP(s2, (TX1)(T1)s1, d, &env->fp_status);\ } =20 +RVVCALL(OPFVF3, vfmacc_vf_h_bf16, OP_UUU_H, H2, H2, fmacc16_bf16) RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16) RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32) RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64) +GEN_VEXT_VF(vfmacc_vf_h_bf16, 2) GEN_VEXT_VF(vfmacc_vf_h, 2) GEN_VEXT_VF(vfmacc_vf_w, 4) GEN_VEXT_VF(vfmacc_vf_d, 8) =20 +static uint16_t fnmacc16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(a, b, d, float_muladd_negate_c | + float_muladd_negate_product, s); +} + static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { return float16_muladd(a, b, d, float_muladd_negate_c | @@ -3485,19 +3570,29 @@ static uint64_t fnmacc64(uint64_t a, uint64_t b, ui= nt64_t d, float_status *s) float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfnmacc_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmacc16_bf16) RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32) RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64) +GEN_VEXT_VV_ENV(vfnmacc_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2) GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4) GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8) +RVVCALL(OPFVF3, vfnmacc_vf_h_bf16, OP_UUU_H, H2, H2, fnmacc16_bf16) RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16) RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32) RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64) +GEN_VEXT_VF(vfnmacc_vf_h_bf16, 2) GEN_VEXT_VF(vfnmacc_vf_h, 2) GEN_VEXT_VF(vfnmacc_vf_w, 4) GEN_VEXT_VF(vfnmacc_vf_d, 8) =20 +static uint16_t fmsac16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(a, b, d, float_muladd_negate_c, s); +} + static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *= s) { return float16_muladd(a, b, d, float_muladd_negate_c, s); @@ -3513,19 +3608,29 @@ static uint64_t fmsac64(uint64_t a, uint64_t b, uin= t64_t d, float_status *s) return float64_muladd(a, b, d, float_muladd_negate_c, s); } =20 +RVVCALL(OPFVV3, vfmsac_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmsac16_bf16) RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16) RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32) RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64) +GEN_VEXT_VV_ENV(vfmsac_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmsac_vv_h, 2) GEN_VEXT_VV_ENV(vfmsac_vv_w, 4) GEN_VEXT_VV_ENV(vfmsac_vv_d, 8) +RVVCALL(OPFVF3, vfmsac_vf_h_bf16, OP_UUU_H, H2, H2, fmsac16_bf16) RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16) RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32) RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64) +GEN_VEXT_VF(vfmsac_vf_h_bf16, 2) GEN_VEXT_VF(vfmsac_vf_h, 2) GEN_VEXT_VF(vfmsac_vf_w, 4) GEN_VEXT_VF(vfmsac_vf_d, 8) =20 +static uint16_t fnmsac16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(a, b, d, float_muladd_negate_product, s); +} + static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { return float16_muladd(a, b, d, float_muladd_negate_product, s); @@ -3541,19 +3646,29 @@ static uint64_t fnmsac64(uint64_t a, uint64_t b, ui= nt64_t d, float_status *s) return float64_muladd(a, b, d, float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfnmsac_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmsac16_bf16) RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16) RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32) RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64) +GEN_VEXT_VV_ENV(vfnmsac_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2) GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4) GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8) +RVVCALL(OPFVF3, vfnmsac_vf_h_bf16, OP_UUU_H, H2, H2, fnmsac16_bf16) RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16) RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32) RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64) +GEN_VEXT_VF(vfnmsac_vf_h_bf16, 2) GEN_VEXT_VF(vfnmsac_vf_h, 2) GEN_VEXT_VF(vfnmsac_vf_w, 4) GEN_VEXT_VF(vfnmsac_vf_d, 8) =20 +static uint16_t fmadd16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(d, b, a, 0, s); +} + static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *= s) { return float16_muladd(d, b, a, 0, s); @@ -3569,19 +3684,30 @@ static uint64_t fmadd64(uint64_t a, uint64_t b, uin= t64_t d, float_status *s) return float64_muladd(d, b, a, 0, s); } =20 +RVVCALL(OPFVV3, vfmadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmadd16_bf16) RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16) RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32) RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64) +GEN_VEXT_VV_ENV(vfmadd_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmadd_vv_h, 2) GEN_VEXT_VV_ENV(vfmadd_vv_w, 4) GEN_VEXT_VV_ENV(vfmadd_vv_d, 8) +RVVCALL(OPFVF3, vfmadd_vf_h_bf16, OP_UUU_H, H2, H2, fmadd16_bf16) RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16) RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32) RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64) +GEN_VEXT_VF(vfmadd_vf_h_bf16, 2) GEN_VEXT_VF(vfmadd_vf_h, 2) GEN_VEXT_VF(vfmadd_vf_w, 4) GEN_VEXT_VF(vfmadd_vf_d, 8) =20 +static uint16_t fnmadd16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(d, b, a, float_muladd_negate_c | + float_muladd_negate_product, s); +} + static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { return float16_muladd(d, b, a, float_muladd_negate_c | @@ -3600,19 +3726,29 @@ static uint64_t fnmadd64(uint64_t a, uint64_t b, ui= nt64_t d, float_status *s) float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfnmadd_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmadd16_bf16) RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32) RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64) +GEN_VEXT_VV_ENV(vfnmadd_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2) GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4) GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8) +RVVCALL(OPFVF3, vfnmadd_vf_h_bf16, OP_UUU_H, H2, H2, fnmadd16_bf16) RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16) RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32) RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64) +GEN_VEXT_VF(vfnmadd_vf_h_bf16, 2) GEN_VEXT_VF(vfnmadd_vf_h, 2) GEN_VEXT_VF(vfnmadd_vf_w, 4) GEN_VEXT_VF(vfnmadd_vf_d, 8) =20 +static uint16_t fmsub16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(d, b, a, float_muladd_negate_c, s); +} + static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *= s) { return float16_muladd(d, b, a, float_muladd_negate_c, s); @@ -3628,19 +3764,29 @@ static uint64_t fmsub64(uint64_t a, uint64_t b, uin= t64_t d, float_status *s) return float64_muladd(d, b, a, float_muladd_negate_c, s); } =20 +RVVCALL(OPFVV3, vfmsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, fmsub16_bf16) RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16) RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32) RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64) +GEN_VEXT_VV_ENV(vfmsub_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmsub_vv_h, 2) GEN_VEXT_VV_ENV(vfmsub_vv_w, 4) GEN_VEXT_VV_ENV(vfmsub_vv_d, 8) +RVVCALL(OPFVF3, vfmsub_vf_h_bf16, OP_UUU_H, H2, H2, fmsub16_bf16) RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16) RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32) RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64) +GEN_VEXT_VF(vfmsub_vf_h_bf16, 2) GEN_VEXT_VF(vfmsub_vf_h, 2) GEN_VEXT_VF(vfmsub_vf_w, 4) GEN_VEXT_VF(vfmsub_vf_d, 8) =20 +static uint16_t fnmsub16_bf16(uint16_t a, uint16_t b, uint16_t d, + float_status *s) +{ + return bfloat16_muladd(d, b, a, float_muladd_negate_product, s); +} + static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status = *s) { return float16_muladd(d, b, a, float_muladd_negate_product, s); @@ -3656,15 +3802,19 @@ static uint64_t fnmsub64(uint64_t a, uint64_t b, ui= nt64_t d, float_status *s) return float64_muladd(d, b, a, float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfnmsub_vv_h_bf16, OP_UUU_H, H2, H2, H2, fnmsub16_bf16) RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16) RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32) RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64) +GEN_VEXT_VV_ENV(vfnmsub_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2) GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4) GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8) +RVVCALL(OPFVF3, vfnmsub_vf_h_bf16, OP_UUU_H, H2, H2, fnmsub16_bf16) RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16) RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32) RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64) +GEN_VEXT_VF(vfnmsub_vf_h_bf16, 2) GEN_VEXT_VF(vfnmsub_vf_h, 2) GEN_VEXT_VF(vfnmsub_vf_w, 4) GEN_VEXT_VF(vfnmsub_vf_d, 8) @@ -3702,6 +3852,15 @@ GEN_VEXT_VV_ENV(vfwmaccbf16_vv, 4) RVVCALL(OPFVF3, vfwmaccbf16_vf, WOP_UUU_H, H4, H2, fwmaccbf16) GEN_VEXT_VF(vfwmaccbf16_vf, 4) =20 +static uint32_t fwnmacc16_bf16(uint16_t a, uint16_t b, uint32_t d, + float_status *s) +{ + return float32_muladd(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), d, + float_muladd_negate_c | float_muladd_negate_prod= uct, + s); +} + static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), @@ -3717,15 +3876,27 @@ static uint64_t fwnmacc32(uint32_t a, uint32_t b, u= int64_t d, float_status *s) float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfwnmacc_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwnmacc16_bf16) RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32) +GEN_VEXT_VV_ENV(vfwnmacc_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 4) GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 8) +RVVCALL(OPFVF3, vfwnmacc_vf_h_bf16, WOP_UUU_H, H4, H2, fwnmacc16_bf16) RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16) RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32) +GEN_VEXT_VF(vfwnmacc_vf_h_bf16, 4) GEN_VEXT_VF(vfwnmacc_vf_h, 4) GEN_VEXT_VF(vfwnmacc_vf_w, 8) =20 +static uint32_t fwmsac16_bf16(uint16_t a, uint16_t b, uint32_t d, + float_status *s) +{ + return float32_muladd(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), d, + float_muladd_negate_c, s); +} + static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status = *s) { return float32_muladd(float16_to_float32(a, true, s), @@ -3740,15 +3911,27 @@ static uint64_t fwmsac32(uint32_t a, uint32_t b, ui= nt64_t d, float_status *s) float_muladd_negate_c, s); } =20 +RVVCALL(OPFVV3, vfwmsac_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwmsac16_bf16) RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32) +GEN_VEXT_VV_ENV(vfwmsac_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwmsac_vv_h, 4) GEN_VEXT_VV_ENV(vfwmsac_vv_w, 8) +RVVCALL(OPFVF3, vfwmsac_vf_h_bf16, WOP_UUU_H, H4, H2, fwmsac16_bf16) RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16) RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32) +GEN_VEXT_VF(vfwmsac_vf_h_bf16, 4) GEN_VEXT_VF(vfwmsac_vf_h, 4) GEN_VEXT_VF(vfwmsac_vf_w, 8) =20 +static uint32_t fwnmsac16_bf16(uint16_t a, uint16_t b, uint32_t d, + float_status *s) +{ + return float32_muladd(bfloat16_to_float32(a, s), + bfloat16_to_float32(b, s), d, + float_muladd_negate_product, s); +} + static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status= *s) { return float32_muladd(float16_to_float32(a, true, s), @@ -3763,12 +3946,16 @@ static uint64_t fwnmsac32(uint32_t a, uint32_t b, u= int64_t d, float_status *s) float_muladd_negate_product, s); } =20 +RVVCALL(OPFVV3, vfwnmsac_vv_h_bf16, WOP_UUU_H, H4, H2, H2, fwnmsac16_bf16) RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32) +GEN_VEXT_VV_ENV(vfwnmsac_vv_h_bf16, 4) GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 4) GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 8) +RVVCALL(OPFVF3, vfwnmsac_vf_h_bf16, WOP_UUU_H, H4, H2, fwnmsac16_bf16) RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) +GEN_VEXT_VF(vfwnmsac_vf_h_bf16, 4) GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) =20 @@ -3874,6 +4061,46 @@ static uint64_t frsqrt7(uint64_t f, int exp_size, in= t frac_size) return val; } =20 +static bfloat16 frsqrt7_h_bf16(bfloat16 f, float_status *s) +{ + int exp_size =3D 8, frac_size =3D 7; + bool sign =3D bfloat16_is_neg(f); + + /* + * frsqrt7(sNaN) =3D canonical NaN + * frsqrt7(-inf) =3D canonical NaN + * frsqrt7(-normal) =3D canonical NaN + * frsqrt7(-subnormal) =3D canonical NaN + */ + if (bfloat16_is_signaling_nan(f, s) || + (bfloat16_is_infinity(f) && sign) || + (bfloat16_is_normal(f) && sign) || + (bfloat16_is_zero_or_denormal(f) && !bfloat16_is_zero(f) && sign))= { + s->float_exception_flags |=3D float_flag_invalid; + return bfloat16_default_nan(s); + } + + /* frsqrt7(qNaN) =3D canonical NaN */ + if (bfloat16_is_quiet_nan(f, s)) { + return bfloat16_default_nan(s); + } + + /* frsqrt7(+-0) =3D +-inf */ + if (bfloat16_is_zero(f)) { + s->float_exception_flags |=3D float_flag_divbyzero; + return bfloat16_set_sign(bfloat16_infinity, sign); + } + + /* frsqrt7(+inf) =3D +0 */ + if (bfloat16_is_infinity(f) && !sign) { + return bfloat16_set_sign(bfloat16_zero, sign); + } + + /* +normal, +subnormal */ + uint64_t val =3D frsqrt7(f, exp_size, frac_size); + return make_float16(val); +} + static float16 frsqrt7_h(float16 f, float_status *s) { int exp_size =3D 5, frac_size =3D 10; @@ -3994,9 +4221,11 @@ static float64 frsqrt7_d(float64 f, float_status *s) return make_float64(val); } =20 +RVVCALL(OPFVV1, vfrsqrt7_v_h_bf16, OP_UU_H, H2, H2, frsqrt7_h_bf16) RVVCALL(OPFVV1, vfrsqrt7_v_h, OP_UU_H, H2, H2, frsqrt7_h) RVVCALL(OPFVV1, vfrsqrt7_v_w, OP_UU_W, H4, H4, frsqrt7_s) RVVCALL(OPFVV1, vfrsqrt7_v_d, OP_UU_D, H8, H8, frsqrt7_d) +GEN_VEXT_V_ENV(vfrsqrt7_v_h_bf16, 2) GEN_VEXT_V_ENV(vfrsqrt7_v_h, 2) GEN_VEXT_V_ENV(vfrsqrt7_v_w, 4) GEN_VEXT_V_ENV(vfrsqrt7_v_d, 8) @@ -4089,6 +4318,38 @@ static uint64_t frec7(uint64_t f, int exp_size, int = frac_size, return val; } =20 +static bfloat16 frec7_h_bf16(bfloat16 f, float_status *s) +{ + int exp_size =3D 8, frac_size =3D 7; + bool sign =3D bfloat16_is_neg(f); + + /* frec7(+-inf) =3D +-0 */ + if (bfloat16_is_infinity(f)) { + return bfloat16_set_sign(bfloat16_zero, sign); + } + + /* frec7(+-0) =3D +-inf */ + if (bfloat16_is_zero(f)) { + s->float_exception_flags |=3D float_flag_divbyzero; + return bfloat16_set_sign(bfloat16_infinity, sign); + } + + /* frec7(sNaN) =3D canonical NaN */ + if (bfloat16_is_signaling_nan(f, s)) { + s->float_exception_flags |=3D float_flag_invalid; + return bfloat16_default_nan(s); + } + + /* frec7(qNaN) =3D canonical NaN */ + if (bfloat16_is_quiet_nan(f, s)) { + return bfloat16_default_nan(s); + } + + /* +-normal, +-subnormal */ + uint64_t val =3D frec7(f, exp_size, frac_size, s); + return make_float16(val); +} + static float16 frec7_h(float16 f, float_status *s) { int exp_size =3D 5, frac_size =3D 10; @@ -4185,36 +4446,46 @@ static float64 frec7_d(float64 f, float_status *s) return make_float64(val); } =20 +RVVCALL(OPFVV1, vfrec7_v_h_bf16, OP_UU_H, H2, H2, frec7_h_bf16) RVVCALL(OPFVV1, vfrec7_v_h, OP_UU_H, H2, H2, frec7_h) RVVCALL(OPFVV1, vfrec7_v_w, OP_UU_W, H4, H4, frec7_s) RVVCALL(OPFVV1, vfrec7_v_d, OP_UU_D, H8, H8, frec7_d) +GEN_VEXT_V_ENV(vfrec7_v_h_bf16, 2) GEN_VEXT_V_ENV(vfrec7_v_h, 2) GEN_VEXT_V_ENV(vfrec7_v_w, 4) GEN_VEXT_V_ENV(vfrec7_v_d, 8) =20 /* Vector Floating-Point MIN/MAX Instructions */ +RVVCALL(OPFVV2, vfmin_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_minimum_nu= mber) RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minimum_number) RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minimum_number) RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minimum_number) +GEN_VEXT_VV_ENV(vfmin_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmin_vv_h, 2) GEN_VEXT_VV_ENV(vfmin_vv_w, 4) GEN_VEXT_VV_ENV(vfmin_vv_d, 8) +RVVCALL(OPFVF2, vfmin_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_minimum_number) RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minimum_number) RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minimum_number) RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minimum_number) +GEN_VEXT_VF(vfmin_vf_h_bf16, 2) GEN_VEXT_VF(vfmin_vf_h, 2) GEN_VEXT_VF(vfmin_vf_w, 4) GEN_VEXT_VF(vfmin_vf_d, 8) =20 +RVVCALL(OPFVV2, vfmax_vv_h_bf16, OP_UUU_H, H2, H2, H2, bfloat16_maximum_nu= mber) RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maximum_number) RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maximum_number) RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maximum_number) +GEN_VEXT_VV_ENV(vfmax_vv_h_bf16, 2) GEN_VEXT_VV_ENV(vfmax_vv_h, 2) GEN_VEXT_VV_ENV(vfmax_vv_w, 4) GEN_VEXT_VV_ENV(vfmax_vv_d, 8) +RVVCALL(OPFVF2, vfmax_vf_h_bf16, OP_UUU_H, H2, H2, bfloat16_maximum_number) RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maximum_number) RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maximum_number) RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maximum_number) +GEN_VEXT_VF(vfmax_vf_h_bf16, 2) GEN_VEXT_VF(vfmax_vf_h, 2) GEN_VEXT_VF(vfmax_vf_w, 4) GEN_VEXT_VF(vfmax_vf_d, 8) @@ -4343,6 +4614,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void= *vs2, \ } \ } =20 +GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h_bf16, uint16_t, H2, bfloat16_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) @@ -4384,10 +4656,17 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, = void *vs2, \ } \ } =20 +GEN_VEXT_CMP_VF(vmfeq_vf_h_bf16, uint16_t, H2, bfloat16_eq_quiet) GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) GEN_VEXT_CMP_VF(vmfeq_vf_w, uint32_t, H4, float32_eq_quiet) GEN_VEXT_CMP_VF(vmfeq_vf_d, uint64_t, H8, float64_eq_quiet) =20 +static bool vmfne16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + FloatRelation compare =3D bfloat16_compare_quiet(a, b, s); + return compare !=3D float_relation_equal; +} + static bool vmfne16(uint16_t a, uint16_t b, float_status *s) { FloatRelation compare =3D float16_compare_quiet(a, b, s); @@ -4406,27 +4685,39 @@ static bool vmfne64(uint64_t a, uint64_t b, float_s= tatus *s) return compare !=3D float_relation_equal; } =20 +GEN_VEXT_CMP_VV_ENV(vmfne_vv_h_bf16, uint16_t, H2, vmfne16_bf16) GEN_VEXT_CMP_VV_ENV(vmfne_vv_h, uint16_t, H2, vmfne16) GEN_VEXT_CMP_VV_ENV(vmfne_vv_w, uint32_t, H4, vmfne32) GEN_VEXT_CMP_VV_ENV(vmfne_vv_d, uint64_t, H8, vmfne64) +GEN_VEXT_CMP_VF(vmfne_vf_h_bf16, uint16_t, H2, vmfne16_bf16) GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) =20 +GEN_VEXT_CMP_VV_ENV(vmflt_vv_h_bf16, uint16_t, H2, bfloat16_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) +GEN_VEXT_CMP_VF(vmflt_vf_h_bf16, uint16_t, H2, bfloat16_lt) GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) =20 +GEN_VEXT_CMP_VV_ENV(vmfle_vv_h_bf16, uint16_t, H2, bfloat16_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) +GEN_VEXT_CMP_VF(vmfle_vf_h_bf16, uint16_t, H2, bfloat16_le) GEN_VEXT_CMP_VF(vmfle_vf_h, uint16_t, H2, float16_le) GEN_VEXT_CMP_VF(vmfle_vf_w, uint32_t, H4, float32_le) GEN_VEXT_CMP_VF(vmfle_vf_d, uint64_t, H8, float64_le) =20 +static bool vmfgt16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + FloatRelation compare =3D bfloat16_compare(a, b, s); + return compare =3D=3D float_relation_greater; +} + static bool vmfgt16(uint16_t a, uint16_t b, float_status *s) { FloatRelation compare =3D float16_compare(a, b, s); @@ -4445,10 +4736,18 @@ static bool vmfgt64(uint64_t a, uint64_t b, float_s= tatus *s) return compare =3D=3D float_relation_greater; } =20 +GEN_VEXT_CMP_VF(vmfgt_vf_h_bf16, uint16_t, H2, vmfgt16_bf16) GEN_VEXT_CMP_VF(vmfgt_vf_h, uint16_t, H2, vmfgt16) GEN_VEXT_CMP_VF(vmfgt_vf_w, uint32_t, H4, vmfgt32) GEN_VEXT_CMP_VF(vmfgt_vf_d, uint64_t, H8, vmfgt64) =20 +static bool vmfge16_bf16(uint16_t a, uint16_t b, float_status *s) +{ + FloatRelation compare =3D bfloat16_compare(a, b, s); + return compare =3D=3D float_relation_greater || + compare =3D=3D float_relation_equal; +} + static bool vmfge16(uint16_t a, uint16_t b, float_status *s) { FloatRelation compare =3D float16_compare(a, b, s); @@ -4470,11 +4769,31 @@ static bool vmfge64(uint64_t a, uint64_t b, float_s= tatus *s) compare =3D=3D float_relation_equal; } =20 +GEN_VEXT_CMP_VF(vmfge_vf_h_bf16, uint16_t, H2, vmfge16_bf16) GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) =20 /* Vector Floating-Point Classify Instruction */ +target_ulong fclass_h_bf16(uint64_t frs1) +{ + bfloat16 f =3D frs1; + bool sign =3D bfloat16_is_neg(f); + + if (bfloat16_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (bfloat16_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (bfloat16_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (bfloat16_is_any_nan(f)) { + float_status s =3D { }; /* for snan_bit_is_one */ + return bfloat16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + target_ulong fclass_h(uint64_t frs1) { float16 f =3D frs1; @@ -4532,9 +4851,11 @@ target_ulong fclass_d(uint64_t frs1) } } =20 +RVVCALL(OPIVV1, vfclass_v_h_bf16, OP_UU_H, H2, H2, fclass_h_bf16) RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) +GEN_VEXT_V(vfclass_v_h_bf16, 2) GEN_VEXT_V(vfclass_v_h, 2) GEN_VEXT_V(vfclass_v_w, 4) GEN_VEXT_V(vfclass_v_d, 8) @@ -4625,17 +4946,21 @@ GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 8) * vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width fl= oat. */ RVVCALL(OPFVV1, vfwcvt_f_xu_v_b, WOP_UU_B, H2, H1, uint8_to_float16) +RVVCALL(OPFVV1, vfwcvt_f_xu_v_b_bf16, WOP_UU_B, H2, H1, uint8_to_bfloat16) RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b, 2) +GEN_VEXT_V_ENV(vfwcvt_f_xu_v_b_bf16, 2) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 8) =20 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ RVVCALL(OPFVV1, vfwcvt_f_x_v_b, WOP_UU_B, H2, H1, int8_to_float16) +RVVCALL(OPFVV1, vfwcvt_f_x_v_b_bf16, WOP_UU_B, H2, H1, int8_to_bfloat16) RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) GEN_VEXT_V_ENV(vfwcvt_f_x_v_b, 2) +GEN_VEXT_V_ENV(vfwcvt_f_x_v_b_bf16, 2) GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 4) GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 8) =20 @@ -4662,17 +4987,21 @@ GEN_VEXT_V_ENV(vfwcvtbf16_f_f_v, 4) #define NOP_UU_W uint32_t, uint64_t, uint64_t /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ RVVCALL(OPFVV1, vfncvt_xu_f_w_b, NOP_UU_B, H1, H2, float16_to_uint8) +RVVCALL(OPFVV1, vfncvt_xu_f_w_b_bf16, NOP_UU_B, H1, H2, bfloat16_to_uint8) RVVCALL(OPFVV1, vfncvt_xu_f_w_h, NOP_UU_H, H2, H4, float32_to_uint16) RVVCALL(OPFVV1, vfncvt_xu_f_w_w, NOP_UU_W, H4, H8, float64_to_uint32) GEN_VEXT_V_ENV(vfncvt_xu_f_w_b, 1) +GEN_VEXT_V_ENV(vfncvt_xu_f_w_b_bf16, 1) GEN_VEXT_V_ENV(vfncvt_xu_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_xu_f_w_w, 4) =20 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer= . */ RVVCALL(OPFVV1, vfncvt_x_f_w_b, NOP_UU_B, H1, H2, float16_to_int8) +RVVCALL(OPFVV1, vfncvt_x_f_w_b_bf16, NOP_UU_B, H1, H2, bfloat16_to_int8) RVVCALL(OPFVV1, vfncvt_x_f_w_h, NOP_UU_H, H2, H4, float32_to_int16) RVVCALL(OPFVV1, vfncvt_x_f_w_w, NOP_UU_W, H4, H8, float64_to_int32) GEN_VEXT_V_ENV(vfncvt_x_f_w_b, 1) +GEN_VEXT_V_ENV(vfncvt_x_f_w_b_bf16, 1) GEN_VEXT_V_ENV(vfncvt_x_f_w_h, 2) GEN_VEXT_V_ENV(vfncvt_x_f_w_w, 4) =20 --=20 2.52.0 From nobody Thu Apr 2 01:29:06 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=sifive.com ARC-Seal: i=1; a=rsa-sha256; t=1772781203; cv=none; d=zohomail.com; s=zohoarc; b=b8V4tVEGvC2elT9Ll6+ge/hpVo86br0GoC/Z52dyA17FoJFKP7G84VyjkGvFgek5pi3ZONIXiTzVW91IE+Gt4KgJtOCNWIEK3ixnZ/GArOQQ0Y9b9Y1XwfcyoV/pLH+7AbxtYfTiW0LNdpw1YUodJbfavWoTJaIBZWNHWoHLRbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1772781203; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bTk7Tk9WP/zMZlQp66wDxav6fYDPL0KXwlM2E2GIdnc=; b=YUv8wkgB8MWJQ7lr6qTvlC/ETa/gjvFpwgRAg553NOzkbGKPLZ4UZtBIZNw6OO8RM/PSblH2XCmW/eezy4eQBZvuXOltrRSVfxTQUs8jACC/Q4Y3hZZiYlzgNtp1MH2xVnRLMZFBaSjonNny/5ltaQodf4HrUymdBFp12hjIE7c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 177278120390481.12273168813101; Thu, 5 Mar 2026 23:13:23 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vyPLc-0003Gd-En; Fri, 06 Mar 2026 02:11:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vyPLT-0003Ex-6x for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:36 -0500 Received: from mail-pf1-x42a.google.com ([2607:f8b0:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vyPLR-0007m4-LK for qemu-devel@nongnu.org; Fri, 06 Mar 2026 02:11:34 -0500 Received: by mail-pf1-x42a.google.com with SMTP id d2e1a72fcca58-82989744ee0so1424225b3a.2 for ; Thu, 05 Mar 2026 23:11:33 -0800 (PST) Received: from duncan.localdomain (114-35-142-126.hinet-ip.hinet.net. [114.35.142.126]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-829a4636c74sm956093b3a.12.2026.03.05.23.11.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2026 23:11:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1772781092; x=1773385892; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bTk7Tk9WP/zMZlQp66wDxav6fYDPL0KXwlM2E2GIdnc=; b=UbNiPRP0eSKeCqGXrIv6dpalKn9Z39hemBXPBWHz1bW5W0Gita7pbdoY/v5tLzIrFj OX4DAXknHI2kNOO++TOb7ysE7EiUN4Jt/um8C6/qe6b/304prolFwkMmlNKzvS7do9e8 RYEVwfTe9LlMSPb/bUEDlnwmp4Iqws7lSJf+qsWR6RLTM8tC9QB79zMF4kg7dKt6Qfst O2MJyJgzyysXivGJzK/XqRLLcVtQ80KvUTWullCe5lp6ovqT0boOOs51cRfW0CW4YTa+ h6QKOwaPUX6+X1Gns/UKYSCFW+MV8uKNJ2YhSlK31WoYi9L5qo74dFUdtWM66Libcupi ZTYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1772781092; x=1773385892; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=bTk7Tk9WP/zMZlQp66wDxav6fYDPL0KXwlM2E2GIdnc=; b=kVgE6vGYTKSwUpVheiDTTJxP1jHbwtWljaXS5JXpgXEvt8uzaw1SM3S9v8DxsOTrq5 JLoaYfR2ZxgxGpVbSrSu5lU+nBYcTfeVDKnu7imszbISwDnSejaFSa35jFdQ+fmVun0s lINBqGJusnuaRxFzroZhbvcsVtwZBP6hb4sdhHNk+0g7pURgMSkUkuioD3ErxcQbzfOv jI+V/F+A4wroFKSMLNs/U17SnC3hPlQRNP/PrmDAInVbDUKdbgmO7xfddvPR/LV8RtxQ 1ICy7lihODenzw2/ftgmGs+18oFyzZyhkXgjg2zRqt1nlG7bbSakr1AvUpuYnRZ2HGOA IFvg== X-Gm-Message-State: AOJu0YwL5FySjxiLOFpAXujg9tJQ1tswr1Q70Katom59pLdv2rWJ74bV Fvsivv2ZCJPUvhPZ3cX24rc36z4apT5y7nBrKZwXQU/XdgpvL/jWGUPCoRM9Vzqgumdy0akYkks 9cIY2zBQzMy0DnUEjyabIwDxDEJdE164Ne5+fnZcUVjcyj7WNuzFcUoZTyr0Fwc1xB8uZ9EHkGD 2xUmHYdxyYUB+g6cLvDOb+sERtLlXBXZM+ZUu4060OguXb X-Gm-Gg: ATEYQzyMtKM7ND8eXYrUYkgLqe8g4H/T7iBvyuJ12grbDs68q6++egIuvf2FbaXBWe4 QrNshHqlvunk+QC2pfoAIOyvFMdDqlqt1F++Ynxk2quVFbXh7LslupoEiri0+jfcx10LNu0SqtQ JEuijndVuOpTVOtXQsufrZDhelUibgTpY5CmKF5aMTmg/dsfM8kmOLCPjcq0srYHBCDD0Zhju8L orblKKcGC3qPYVZDUizw/zVfYtmWzfYpXi0Ug1S4t3GHt7ucaba9GOkImdnpc7VfDVh+CJFxO6h 9+xyaz3fyXzETrlVh/9todezmu+QdMBJWj73lgXfZlAKHmIJcjXK/lokKxkb1rw1JPafeObgY/a BGjaJYjlFjmtr5thYvDq0wi0ELeOic1hjurjL2EJYA1eLX6KzAef2Qw7AIrYl3x0bP9Lb50EnbZ n5QJXmd/5kGDSeL6QRh8Eh4vxS/XUWs35P7ZN7zTFuXcuRqb+Hm2izRPYTFt2d+bXWLpuQW5kle TdQkwzhk65u6UkMzjRGe0NlBsl7NVfonqrQVA== X-Received: by 2002:a05:6a00:249b:b0:827:3e19:574a with SMTP id d2e1a72fcca58-829a2f14307mr949536b3a.42.1772781091994; Thu, 05 Mar 2026 23:11:31 -0800 (PST) From: Max Chou To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Chao Liu , Max Chou Subject: [PATCH v5 9/9] target/riscv: Expose Zvfbfa extension as an experimental cpu property Date: Fri, 6 Mar 2026 15:11:04 +0800 Message-ID: <20260306071105.3328365-10-max.chou@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260306071105.3328365-1-max.chou@sifive.com> References: <20260306071105.3328365-1-max.chou@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=max.chou@sifive.com; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1772781205409154100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Daniel Henrique Barboza Reviewed-by: Chao Liu Signed-off-by: Max Chou --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 376517755e..73cfcbdf6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1379,6 +1379,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = =3D { /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] =3D { MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), + MULTI_EXT_CFG_BOOL("x-zvfbfa", ext_zvfbfa, false), =20 { }, }; --=20 2.52.0