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a="91448343" X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="91448343" X-CSE-ConnectionGUID: DNBX2CNzQiaFPYy1vJik6Q== X-CSE-MsgGUID: WYycjowlRsqNj+OEtUFvow== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,104,1770624000"; d="scan'208";a="215613452" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, xudong.hao@intel.com, Zhenzhong Duan Subject: [PATCH v1 12/13] intel_iommu_accel: Add pasid bits size check Date: Thu, 5 Mar 2026 22:44:06 -0500 Message-ID: <20260306034409.184873-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260306034409.184873-1-zhenzhong.duan@intel.com> References: <20260306034409.184873-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772768804373154100 Content-Type: text/plain; charset="utf-8" If pasid bits size is bigger than host side, host could fail to emulate all bindings in guest. Add a check to fail device plug early. Pasid bits size should also be no more than 20 bits according to PCI spec. Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 5 +++++ hw/i386/intel_iommu_accel.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index ede4db6d2d..d6674861fd 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -196,6 +196,7 @@ #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_NWFS (1ULL << 33) #define VTD_ECAP_SET_PSS(x, v) ((x)->ecap =3D deposit64((x)->ecap, 35= , 5, v)) +#define VTD_ECAP_PSS(ecap) extract64(ecap, 35, 5) #define VTD_ECAP_PASID (1ULL << 40) #define VTD_ECAP_PDS (1ULL << 42) #define VTD_ECAP_SMTS (1ULL << 43) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3ea5b92b34..e99a9cf9c6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5559,6 +5559,11 @@ static bool vtd_decide_config(IntelIOMMUState *s, Er= ror **errp) error_setg(errp, "Need to set scalable mode for PASID"); return false; } + if (s->pasid > PCI_EXT_CAP_PASID_MAX_WIDTH) { + error_setg(errp, "PASID width %d, exceed Max PASID Width %d allowe= d " + "in PCI spec", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH); + return false; + } =20 if (s->svm) { if (!x86_iommu->dt_supported) { diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index acb1b1e238..15412123d5 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -44,6 +44,7 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMM= UDevice *vtd_hiod, HostIOMMUDevice *hiod =3D vtd_hiod->hiod; struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + uint8_t hpasid =3D VTD_ECAP_PSS(vtd->ecap_reg) + 1; PCIBus *bus =3D vtd_hiod->bus; PCIDevice *pdev =3D bus->devices[vtd_hiod->devfn]; =20 @@ -64,6 +65,13 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOM= MUDevice *vtd_hiod, return false; } =20 + /* Only do the check when host device support PASIDs */ + if (caps->max_pasid_log2 && s->pasid > hpasid) { + error_setg(errp, "PASID bits size %d > host IOMMU PASID bits size = %d", + s->pasid, hpasid); + return false; + } + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { error_setg(errp, "Host device downstream to a PCI bridge is " "unsupported when x-flts=3Don"); --=20 2.47.3