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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772733480; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=RVEiLOdGDPNHRwZDNO82s6pqTz6mXa9i/G3X+jt04ng=; b=FYlCFBR2DCOx1CAynveqaUWaH/JLeaW7ergP7AXZfUk41i2tyrLaKVGZ09/O900JbqigVX 5OAKXYyech/kq5mv6h+D4we4FPCQN0IeHT87/9rlucwGOb0gxOrNRHPIMgoQ//e7y0fx78 Cg5hdCKnhFeyKZoUCHhwbNFHkJJz8Kc= X-MC-Unique: Uc9tyuarMXOU7xW469-OMw-1 X-Mimecast-MFC-AGG-ID: Uc9tyuarMXOU7xW469-OMw_1772733471 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Joe Komlodi , Patrick Venture , Hao Wu , Jithu Joseph , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/38] hw/i3c/dw-i3c: Add IRQ MMIO behavior Date: Thu, 5 Mar 2026 18:56:46 +0100 Message-ID: <20260305175711.1119025-14-clg@redhat.com> In-Reply-To: <20260305175711.1119025-1-clg@redhat.com> References: <20260305175711.1119025-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1772733768735154100 From: Jamin Lin Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Reviewed-by: Hao Wu Reviewed-by: Jamin Lin Signed-off-by: Jamin Lin Tested-by: Jithu Joseph Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-13-jamin_li= n@aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/i3c/dw-i3c.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c index 7ca99fb87e44..0b99c7edfbfd 100644 --- a/hw/i3c/dw-i3c.c +++ b/hw/i3c/dw-i3c.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include "migration/vmstate.h" #include "trace.h" +#include "hw/core/irq.h" =20 REG32(DEVICE_CTRL, 0x00) FIELD(DEVICE_CTRL, I3C_BROADCAST_ADDR_INC, 0, 1) @@ -335,6 +336,46 @@ static const uint32_t dw_i3c_ro[DW_I3C_NR_REGS] =3D { [R_SLAVE_CONFIG] =3D 0xffffffff, }; =20 +static void dw_i3c_update_irq(DWI3C *s) +{ + bool level =3D !!(s->regs[R_INTR_SIGNAL_EN] & s->regs[R_INTR_STATUS]); + qemu_set_irq(s->irq, level); +} + +static uint32_t dw_i3c_intr_status_r(DWI3C *s) +{ + /* Only return the status whose corresponding EN bits are set. */ + return s->regs[R_INTR_STATUS] & s->regs[R_INTR_STATUS_EN]; +} + +static void dw_i3c_intr_status_w(DWI3C *s, uint32_t val) +{ + /* INTR_STATUS[13:5] is w1c, other bits are RO. */ + val &=3D 0x3fe0; + s->regs[R_INTR_STATUS] &=3D ~val; + + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_status_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_STATUS_EN] =3D val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_signal_en_w(DWI3C *s, uint32_t val) +{ + s->regs[R_INTR_SIGNAL_EN] =3D val; + dw_i3c_update_irq(s); +} + +static void dw_i3c_intr_force_w(DWI3C *s, uint32_t val) +{ + /* INTR_FORCE is WO, just set the corresponding INTR_STATUS bits. */ + s->regs[R_INTR_STATUS] =3D val; + dw_i3c_update_irq(s); +} + static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size) { DWI3C *s =3D DW_I3C(opaque); @@ -348,6 +389,9 @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset= , unsigned size) case R_INTR_FORCE: value =3D 0; break; + case R_INTR_STATUS: + value =3D dw_i3c_intr_status_r(s); + break; default: value =3D s->regs[addr]; break; @@ -392,6 +436,18 @@ static void dw_i3c_write(void *opaque, hwaddr offset, = uint64_t value, break; case R_RESET_CTRL: break; + case R_INTR_STATUS: + dw_i3c_intr_status_w(s, val32); + break; + case R_INTR_STATUS_EN: + dw_i3c_intr_status_en_w(s, val32); + break; + case R_INTR_SIGNAL_EN: + dw_i3c_intr_signal_en_w(s, val32); + break; + case R_INTR_FORCE: + dw_i3c_intr_force_w(s, val32); + break; default: s->regs[addr] =3D val32; break; --=20 2.53.0