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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1772733467; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=47an3b/PQ2lQdrCnKgF9UWsrwpElW+uBBwdjpJ1uWKY=; b=He1DmxtiesdRN00S8ZkIneJ9/UnASvB4poLhQ05WAqntw+ETNiuNM6e84lMuTopYMu85+s jGH4D1AZPWHVa1x7vLPXirAqQ4fWYRUXlPrIGq2FW6IoMLZa9icf3WSxdQFpQDh6obSxn+ v9G7Q0LyFkhovgsl4UJaEGnD4q6Yq7o= X-MC-Unique: IxElKDkyP-a__0Od9lPJhg-1 X-Mimecast-MFC-AGG-ID: IxElKDkyP-a__0Od9lPJhg_1772733459 From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jamin Lin , Joe Komlodi , Patrick Venture , Jithu Joseph , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/38] hw/i3c/aspeed_i3c: Add register RO field masks Date: Thu, 5 Mar 2026 18:56:42 +0100 Message-ID: <20260305175711.1119025-10-clg@redhat.com> In-Reply-To: <20260305175711.1119025-1-clg@redhat.com> References: <20260305175711.1119025-1-clg@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1772733628424154100 From: Jamin Lin Adds read-only register masks for the Aspeed I3C controller registers. Signed-off-by: Joe Komlodi Reviewed-by: Patrick Venture Signed-off-by: Jamin Lin Tested-by: Jithu Joseph Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-9-jamin_lin= @aspeedtech.com Signed-off-by: C=C3=A9dric Le Goater --- hw/i3c/aspeed_i3c.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/i3c/aspeed_i3c.c b/hw/i3c/aspeed_i3c.c index a21570028887..2700c5f4cdeb 100644 --- a/hw/i3c/aspeed_i3c.c +++ b/hw/i3c/aspeed_i3c.c @@ -74,6 +74,21 @@ REG32(I3C6_REG1, 0x64) FIELD(I3C6_REG1, SA_EN, 15, 1) FIELD(I3C6_REG1, INST_ID, 16, 4) =20 +static const uint32_t ast2600_i3c_controller_ro[ASPEED_I3C_NR_REGS] =3D { + [R_I3C1_REG0] =3D 0xcc000000, + [R_I3C1_REG1] =3D 0xfff00000, + [R_I3C2_REG0] =3D 0xcc000000, + [R_I3C2_REG1] =3D 0xfff00000, + [R_I3C3_REG0] =3D 0xcc000000, + [R_I3C3_REG1] =3D 0xfff00000, + [R_I3C4_REG0] =3D 0xcc000000, + [R_I3C4_REG1] =3D 0xfff00000, + [R_I3C5_REG0] =3D 0xcc000000, + [R_I3C5_REG1] =3D 0xfff00000, + [R_I3C6_REG0] =3D 0xcc000000, + [R_I3C6_REG1] =3D 0xfff00000, +}; + static uint64_t aspeed_i3c_read(void *opaque, hwaddr addr, unsigned int si= ze) { AspeedI3CState *s =3D ASPEED_I3C(opaque); @@ -97,6 +112,7 @@ static void aspeed_i3c_write(void *opaque, =20 addr >>=3D 2; =20 + data &=3D ~ast2600_i3c_controller_ro[addr]; /* I3C controller register */ switch (addr) { case R_I3C1_REG1: --=20 2.53.0