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Thu, 5 Mar 2026 06:09:37 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1CA9F58058; Thu, 5 Mar 2026 06:09:36 +0000 (GMT) Received: from gfwr526.rchland.ibm.com (unknown [9.10.239.119]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 5 Mar 2026 06:09:36 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=rlVmvqf7TTqxevRDS H6/7XkYiRxu/TeAU/Po896My0E=; b=n5Y2jy/hIrfmob7+idzlFVZY7IiHcRj59 4eHoZqGjOXDgDRKpAsKYWwevCU9SbNBMZ+t7d3DHOFpW4iY2oi7KKqpQtYA0jBkv jJV6jXzEdtjmSaSz1En4vwk87OTjEhW2I9milXAQD8ZzRCoXTArwV804wS7Ag5ox v0aBVzkqL7mPP48fuOBJh2vTkR9SSKcMUVGT8pAs+jTj0BxJzjD01ri2xJhE/qQK KbLWrr8Tgr5YYnTZIgNV4i00hPYwQtVogOd+CvWv4bbNw2aHC3Q8wqT+VXrC4IEI R1/Gb7JJwGlVG4y4qWLNJGrYIwbB86YZkhlx60QDYsk/bszuG6wuA== From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v4 6/9] pnv/phb4: Set link-active status in HPSTAT and LMR registers Date: Thu, 5 Mar 2026 00:09:08 -0600 Message-ID: <20260305060923.3753402-7-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA0NiBTYWx0ZWRfX72z8yGDF745i MbKlAN6jFvXeWI2G1dzXSDA73fs1qu1SwP79WoFemsucI5vaWpHbJ7mgWLGKXvECazxlBM8eqKd BJSQlz8sGecBeJxxnLZb4vUcPg3BKfkQQ+2Wz3UMO1AKhBcOt05itLeJO9/WCztU4g7Pg1ygJeh zkEUKmsLeRMGRF2wHY9prshNPFQEDbj2DEGpAS5D795wChOla4YPgtQnH0ehQfLR8m+8wjuHkXy cgUarPs5Ml5yWAFS3qvoAX5WojCitdqeXUm9EUFmCleaw5Z/rqV2z2rK8zzeAIb5IEEPHzd1RET JoCDGjMLk7F+6PqCEyDiqXQEzVUiR154mJ3ppBFQlIogZYcvetmqORmnazqMILVicnOlZHZOPEl 69tDDxY9HoH9Bl8L4inm5y0ayl3hMLmw+Inwl3CiYkPx9GhEU3xAkqqngTjC/A4gLeBxab9wBsh ByCr8F2GRdlqtpcadvQ== X-Proofpoint-ORIG-GUID: iUYdCPQtGKFkpqkqBQO7kWf8UVXkRrT7 X-Proofpoint-GUID: 4XjDsMEv8Lr4vB0NC9uJcq3L4-JpPhY8 X-Authority-Analysis: v=2.4 cv=AobjHe9P c=1 sm=1 tr=0 ts=69a91e24 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=20KFwNOVAAAA:8 a=SX2aUA2rIF85faSKF8YA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_01,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050046 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Config-read the link-status register in the PCI-E macro, Depending on the link-active bit, set the link-active status in the HOTPLUG_STATUS and LINK_MANAGEMENT registers Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg after config-reading the slot-status in the PCI-E macro. Signed-off-by: Saif Abrar Reviewed-by: Michael S. Tsirkin --- v4: Variables declaration moved to the top of the method pnv_phb4_reg_read(= ). v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 59 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 25539b7c32..c35f632e64 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -511,6 +511,20 @@ static uint32_t get_exp_offset(PCIDevice *pdev) return rpc->exp_offset; } =20 +/* + * Config-read the link-status register in the PCI-E macro, + * convert to LE and check the link-active bit. + */ +static uint32_t is_link_active(PnvPHB4 *phb) +{ + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); + PCIDevice *pdev =3D pci_find_device(pci->bus, 0, 0); + uint32_t exp_offset =3D get_exp_offset(pdev); + + return (bswap32(pnv_phb4_rc_config_read(phb, exp_offset + PCI_EXP_LNKS= TA, 4) + ) & PCI_EXP_LNKSTA_DLLLA); +} + /* * Apply sticky-mask 's' to the reset-value 'v' and write to the address '= a'. * RC-config space values and masks are LE. @@ -729,6 +743,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, val =3D 0; break; =20 + case PHB_PCIE_HOTPLUG_STATUS: + /* For normal operations, Simspeed diagnostic bit is always zero */ + val &=3D PHB_PCIE_HPSTAT_SIMDIAG; + break; + /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: case PHB_ETU_ERR_SUMMARY: @@ -876,6 +895,10 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) { PnvPHB4 *phb =3D PNV_PHB4(opaque); + /* Get the PCI-E capability offset from the root-port */ + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); + PCIDevice *pdev =3D pci_find_device(pci->bus, 0, 0); + uint32_t exp_base =3D get_exp_offset(pdev); uint64_t val; =20 if ((off & 0xfffc) =3D=3D PHB_CONFIG_DATA) { @@ -944,8 +967,37 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr= off, unsigned size) val |=3D PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; return val; =20 + /* + * Read PCI-E registers and set status for: + * - Card present (active low bit 10) + * - Link active (bit 12) + */ case PHB_PCIE_HOTPLUG_STATUS: - /* Clear write-only bit */ + /* + * Presence-status bit hpi_present_n is active-low, with reset val= ue 1. + * Start by setting this bit to 1, indicating the card is not pres= ent. + * Then check the PCI-E register and clear the bit if card is pres= ent. + */ + val |=3D PHB_PCIE_HPSTAT_PRESENCE; + + /* + * Config-read the PCI-E macro register for slot-status. + * Method for config-read converts to BE value. + * To check actual bit in the PCI-E register, + * convert the value back to LE using bswap32(). + * Clear the Presence-status active low bit. + */ + if (bswap32(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA= , 4)) + & PCI_EXP_SLTSTA_PDS) { + val &=3D ~PHB_PCIE_HPSTAT_PRESENCE; + } + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |=3D PHB_PCIE_HPSTAT_LINKACTIVE; + } + + /* Clear write-only resample-bit */ val &=3D ~PHB_PCIE_HPSTAT_RESAMPLE; return val; =20 @@ -953,6 +1005,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwadd= r off, unsigned size) case PHB_PCIE_LMR: /* These write-only bits always read as 0 */ val &=3D ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |=3D PHB_PCIE_LMR_LINKACTIVE; + } return val; =20 /* Silent simple reads */ --=20 2.47.3