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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691082941139100 New qtest testbench added for PHB[345]. Testbench reads PHB Version register and asserts that bits[24:31] have value 0xA3, 0xA4 and 0xA5 respectively. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater --- v3: Updates for coding guidelines. v2: Added version check for PHB3 and PHB4 also. tests/qtest/meson.build | 1 + tests/qtest/pnv-phb4-test.c | 98 +++++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100644 tests/qtest/pnv-phb4-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index ba9f59d2f8..030f3f4fc6 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -182,6 +182,7 @@ qtests_ppc64 =3D \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xive2-test'] : [])= + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-spi-seeprom-test']= : []) + \ (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] : = []) + \ + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb4-test'] : []) = + \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) + = \ (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) + = \ (slirp.found() ? ['pxe-test'] : []) + \ diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c new file mode 100644 index 0000000000..797f6b6c87 --- /dev/null +++ b/tests/qtest/pnv-phb4-test.c @@ -0,0 +1,98 @@ +/* + * QTest testcase for PowerNV PHB4 + * + * Copyright (c) 2025, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + */ + +#include "qemu/osdep.h" +#include "libqtest.h" +#include "hw/pci-host/pnv_phb4_regs.h" +#include "pnv-xscom.h" + +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) + +#define PHB3_PBCQ_SPCI_ASB_ADDR 0x0 +#define PHB3_PBCQ_SPCI_ASB_DATA 0x2 + +/* Index of PNV_CHIP_POWER10 in pnv_chips[] within "pnv-xscom.h" */ +#define PNV_P10_CHIP_INDEX 3 +#define PHB4_XSCOM 0x40084800ull + +/* + * Indirect XSCOM read:: + * - Write 'Indirect Address Register' with register-offset to read. + * - Read 'Indirect Data Register' to get the value. + */ +static uint64_t pnv_phb_xscom_read(QTestState *qts, const PnvChip *chip, + uint64_t scom, uint32_t indirect_addr, uint32_t indirect_data, + uint64_t reg) +{ + qtest_writeq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_addr), r= eg); + return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_da= ta)); +} + +/* Assert that 'PHB - Version Register' bits[24:31] are as expected */ +static void phb_version_test(const void *data) +{ + const PnvChip *chip =3D (PnvChip *)data; + QTestState *qts; + const char *machine =3D "powernv8"; + uint64_t phb_xscom =3D 0x4809e000; + uint64_t reg_phb_version =3D PHB_VERSION; + uint32_t indirect_addr =3D PHB3_PBCQ_SPCI_ASB_ADDR; + uint32_t indirect_data =3D PHB3_PBCQ_SPCI_ASB_DATA; + uint32_t expected_ver =3D 0xA3; + uint64_t ver; + + if (chip->chip_type =3D=3D PNV_CHIP_POWER9) { + machine =3D "powernv9"; + phb_xscom =3D 0x68084800; + indirect_addr =3D PHB_SCOM_HV_IND_ADDR; + indirect_data =3D PHB_SCOM_HV_IND_DATA; + reg_phb_version |=3D PPC_BIT(0); + expected_ver =3D 0xA4; + } else if (chip->chip_type =3D=3D PNV_CHIP_POWER10) { + machine =3D "powernv10"; + phb_xscom =3D PHB4_XSCOM; + indirect_addr =3D PHB_SCOM_HV_IND_ADDR; + indirect_data =3D PHB_SCOM_HV_IND_DATA; + reg_phb_version |=3D PPC_BIT(0); + expected_ver =3D 0xA5; + } + + qts =3D qtest_initf("-M %s -accel tcg -cpu %s", machine, chip->cpu_mod= el); + + ver =3D pnv_phb_xscom_read(qts, chip, phb_xscom, + indirect_addr, indirect_data, reg_phb_vers= ion); + + /* PHB Version register bits [24:31] */ + ver =3D ver >> (63 - 31); + g_assert_cmpuint(ver, =3D=3D, expected_ver); + + qtest_quit(qts); +} + +/* Verify versions of all supported PHB's */ +static void add_phbX_version_test(void) +{ + for (int i =3D 0; i < ARRAY_SIZE(pnv_chips); i++) { + char *tname =3D g_strdup_printf("pnv-phb/%s", + pnv_chips[i].cpu_model); + qtest_add_data_func(tname, &pnv_chips[i], phb_version_test); + g_free(tname); + } +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + /* PHB[345] tests */ + add_phbX_version_test(); + + return g_test_run(); +} --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691082866139100 Add a method to be invoked on QEMU reset. Also add CFG and PBL core-blocks reset logic using appropriate bits of PHB_PCIE_CRESET register. Tested by reading the reset value of a register. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Michael S. Tsirkin --- v3: Updates for coding guidelines. v2: - Using the ResettableClass. - Reset of the root complex registers done in pnv_phb_root_port_reset_hold(= ). hw/pci-host/pnv_phb.c | 1 + hw/pci-host/pnv_phb4.c | 103 +++++++++++++++++++++++++++- include/hw/pci-host/pnv_phb4.h | 1 + include/hw/pci-host/pnv_phb4_regs.h | 16 ++++- tests/qtest/pnv-phb4-test.c | 28 +++++++- 5 files changed, 145 insertions(+), 4 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 0b556d1bf5..d4f452d7b2 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -232,6 +232,7 @@ static void pnv_phb_root_port_reset_hold(Object *obj, R= esetType type) pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); pci_config_set_interrupt_pin(conf, 0); + pnv_phb4_cfg_core_reset(d); } =20 static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 396bc47817..763e9c9776 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1,7 +1,8 @@ /* * QEMU PowerPC PowerNV (POWER9) PHB4 model + * QEMU PowerPC PowerNV (POWER10) PHB5 model * - * Copyright (c) 2018-2020, IBM Corporation. + * Copyright (c) 2018-2025, IBM Corporation. * * This code is licensed under the GPL version 2 or later. See the * COPYING file in the top-level directory. @@ -22,6 +23,7 @@ #include "hw/core/qdev-properties.h" #include "qom/object.h" #include "trace.h" +#include "system/reset.h" =20 #define phb_error(phb, fmt, ...) \ qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ @@ -499,6 +501,81 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) } } =20 +/* + * Get the PCI-E capability offset from the root-port + */ +static uint32_t get_exp_offset(PCIDevice *pdev) +{ + PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(pdev); + + return rpc->exp_offset; +} + +void pnv_phb4_cfg_core_reset(PCIDevice *d) +{ + uint8_t *conf =3D d->config; + uint32_t exp_offset =3D get_exp_offset(d); + + pci_set_word(conf + PCI_COMMAND, PCI_COMMAND_SERR); + pci_set_word(conf + PCI_STATUS, PCI_STATUS_CAP_LIST); + pci_set_long(conf + PCI_CLASS_REVISION, 0x06040000); + pci_set_long(conf + PCI_CACHE_LINE_SIZE, BIT(16)); + pci_set_word(conf + PCI_MEMORY_BASE, BIT(4)); + pci_set_word(conf + PCI_PREF_MEMORY_BASE, BIT(0) | BIT(4)); + pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, PCI_PREF_RANGE_TYPE_64); + pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6)); + pci_set_long(conf + PCI_CAPABILITY_LIST, BIT(6)); + pci_set_word(conf + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_SERR); + pci_set_long(conf + PCI_BRIDGE_CONTROL + PCI_PM_PMC, 0xC8034801); + + pci_set_long(conf + exp_offset, 0x420010); + pci_set_long(conf + exp_offset + PCI_EXP_DEVCAP, 0x8022); + pci_set_long(conf + exp_offset + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_EXT_TAG + | PCI_EXP_DEVCTL_PAYLOAD_512= B); + pci_set_long(conf + exp_offset + PCI_EXP_LNKCAP, PCI_EXP_LNKCAP_LBNC + | PCI_EXP_LNKCAP_DLLLARC | BIT(8) | PCI_EXP_LNKCAP_SLS_32= _0GB); + pci_set_word(conf + exp_offset + PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_RCB); + pci_set_word(conf + exp_offset + PCI_EXP_LNKSTA, + (PCI_EXP_LNKSTA_NLW_X8 << 2) | PCI_EXP_LNKSTA_CLS_2= _5GB); + pci_set_long(conf + exp_offset + PCI_EXP_SLTCTL, + PCI_EXP_SLTCTL_ASPL_DIS= ABLE); + pci_set_long(conf + exp_offset + PCI_EXP_DEVCAP2, BIT(16) + | PCI_EXP_DEVCAP2_ARI | PCI_EXP_DEVCAP2_COMP_TMOUT_DIS |= 0xF); + pci_set_long(conf + exp_offset + PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_ARI); + pci_set_long(conf + exp_offset + PCI_EXP_LNKCAP2, BIT(23) + | PCI_EXP_LNKCAP2_SLS_32_0GB + | PCI_EXP_LNKCAP2_SLS_16_0GB | PCI_EXP_LNKCAP2_SLS_= 8_0GB + | PCI_EXP_LNKCAP2_SLS_5_0GB | PCI_EXP_LNKCAP2_SLS_2= _5GB); + pci_set_long(conf + PHB_AER_ECAP, PCI_EXT_CAP(0x1, 0x1, 0x148)); + pci_set_long(conf + PHB_SEC_ECAP, (0x1A0 << 20) | BIT(16) + | PCI_EXT_CAP_ID_SE= CPCI); + pci_set_long(conf + PHB_LMR_ECAP, 0x1E810027); + /* LMR - Margining Lane Control / Status Register # 2 to 16 */ + for (int i =3D PHB_LMR_CTLSTA_2 ; i <=3D PHB_LMR_CTLSTA_16 ; i +=3D 4)= { + pci_set_long(conf + i, 0x9C38); + } + + pci_set_long(conf + PHB_DLF_ECAP, 0x1F410025); + pci_set_long(conf + PHB_DLF_CAP, 0x80000001); + pci_set_long(conf + P16_ECAP, 0x22410026); + pci_set_long(conf + P32_ECAP, 0x1002A); + pci_set_long(conf + P32_CAP, 0x103); +} + +static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb) +{ + /* Zero all registers initially */ + for (int i =3D PHB_PBL_CONTROL ; i <=3D PHB_PBL_ERR1_STATUS_MASK ; i += =3D 8) { + phb->regs[i >> 3] =3D 0x0; + } + + /* Set specific register values */ + phb->regs[PHB_PBL_CONTROL >> 3] =3D 0xC009000000000000; + phb->regs[PHB_PBL_TIMEOUT_CTRL >> 3] =3D 0x2020000000000000; + phb->regs[PHB_PBL_NPTAG_ENABLE >> 3] =3D 0xFFFFFFFF00000000; + phb->regs[PHB_PBL_SYS_LINK_INIT >> 3] =3D 0x80088B4642473000; +} + static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, unsigned size) { @@ -612,6 +689,18 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, pnv_phb4_update_xsrc(phb); break; =20 + /* Reset core blocks */ + case PHB_PCIE_CRESET: + if (val & PHB_PCIE_CRESET_CFG_CORE) { + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); + + pnv_phb4_cfg_core_reset(pci_find_device(pci->bus, 0, 0)); + } + if (val & PHB_PCIE_CRESET_PBL) { + pnv_phb4_pbl_core_reset(phb); + } + break; + /* Silent simple writes */ case PHB_ASN_CMPM: case PHB_CONFIG_ADDRESS: @@ -1532,6 +1621,13 @@ static PCIIOMMUOps pnv_phb4_iommu_ops =3D { .get_address_space =3D pnv_phb4_dma_iommu, }; =20 +static void pnv_phb4_reset(Object *obj, ResetType type) +{ + PnvPHB4 *phb =3D PNV_PHB4(obj); + + pnv_phb4_pbl_core_reset(phb); +} + static void pnv_phb4_instance_init(Object *obj) { PnvPHB4 *phb =3D PNV_PHB4(obj); @@ -1608,6 +1704,8 @@ static void pnv_phb4_realize(DeviceState *dev, Error = **errp) phb->qirqs =3D qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_= irqs); =20 pnv_phb4_xscom_realize(phb); + + qemu_register_resettable(OBJECT(dev)); } =20 /* @@ -1701,12 +1799,15 @@ static void pnv_phb4_class_init(ObjectClass *klass,= const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); XiveNotifierClass *xfc =3D XIVE_NOTIFIER_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->realize =3D pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); dc->user_creatable =3D false; =20 xfc->notify =3D pnv_phb4_xive_notify; + + rc->phases.enter =3D pnv_phb4_reset; } =20 static const TypeInfo pnv_phb4_type_info =3D { diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index de996e718b..47a5c3edf5 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -160,6 +160,7 @@ void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf= ); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp); void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb); +void pnv_phb4_cfg_core_reset(PCIDevice *d); extern const MemoryRegionOps pnv_phb4_xscom_ops; =20 /* diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_= phb4_regs.h index bea96f4d91..6892e21cc9 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -343,6 +343,18 @@ #define PHB_RC_CONFIG_BASE 0x1000 #define PHB_RC_CONFIG_SIZE 0x800 =20 +#define PHB_AER_ECAP 0x100 +#define PHB_AER_CAPCTRL 0x118 +#define PHB_SEC_ECAP 0x148 +#define PHB_LMR_ECAP 0x1A0 +#define PHB_LMR_CTLSTA_2 0x1AC +#define PHB_LMR_CTLSTA_16 0x1E4 +#define PHB_DLF_ECAP 0x1E8 +#define PHB_DLF_CAP 0x1EC +#define P16_ECAP 0x1F4 +#define P32_ECAP 0x224 +#define P32_CAP 0x228 + /* PHB4 REGB registers */ =20 /* PBL core */ @@ -368,7 +380,7 @@ #define PHB_PCIE_SCR 0x1A00 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) - +#define PHB_PCIE_BNR 0x1A08 =20 #define PHB_PCIE_CRESET 0x1A10 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) @@ -423,6 +435,8 @@ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 +#define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40 +#define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98 =20 /* Error */ #define PHB_REGB_ERR_STATUS 0x1C00 diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 797f6b6c87..8cd6c1bc59 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -35,6 +35,29 @@ static uint64_t pnv_phb_xscom_read(QTestState *qts, cons= t PnvChip *chip, return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_da= ta)); } =20 +#define PHB4_XSCOM_READ(a) pnv_phb_xscom_read(qts, \ + &pnv_chips[PNV_P10_CHIP_INDEX], PHB4_XS= COM, \ + PHB_SCOM_HV_IND_ADDR, PHB_SCOM_HV_IND_D= ATA, \ + PPC_BIT(0) | (a)) + +/* Assert that 'PHB PBL Control' register has correct reset value */ +static void phb4_reset_test(QTestState *qts) +{ + g_assert_cmpuint(PHB4_XSCOM_READ(PHB_PBL_CONTROL), =3D=3D, 0xC00900000= 0000000); +} + +static void phb4_tests(void) +{ + QTestState *qts =3D NULL; + + qts =3D qtest_initf("-machine powernv10 -accel tcg"); + + /* Check reset value of a register */ + phb4_reset_test(qts); + + qtest_quit(qts); +} + /* Assert that 'PHB - Version Register' bits[24:31] are as expected */ static void phb_version_test(const void *data) { @@ -72,8 +95,6 @@ static void phb_version_test(const void *data) /* PHB Version register bits [24:31] */ ver =3D ver >> (63 - 31); g_assert_cmpuint(ver, =3D=3D, expected_ver); - - qtest_quit(qts); } =20 /* Verify versions of all supported PHB's */ @@ -94,5 +115,8 @@ int main(int argc, char **argv) /* PHB[345] tests */ add_phbX_version_test(); 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charset="utf-8" Sticky bits retain their values on reset and are not overwritten with the reset value. Added sticky reset logic for all required registers, i.e. CFG core, PBL core, PHB error registers, PCIE stack registers and REGB error registers. Tested by writing all 1's to the reg PHB_PBL_ERR_INJECT. This will set the bits in the reg PHB_PBL_ERR_STATUS. Reset the PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESET. Verify that the sticky bits in the PHB_PBL_ERR_STATUS reg are still set. Signed-off-by: Saif Abrar --- v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 123 +++++++++++++++++++++++++++- include/hw/pci-host/pnv_phb4_regs.h | 20 ++++- tests/qtest/pnv-phb4-test.c | 41 ++++++++++ 3 files changed, 179 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 763e9c9776..b3f46f7fe1 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -511,6 +511,18 @@ static uint32_t get_exp_offset(PCIDevice *pdev) return rpc->exp_offset; } =20 +/* + * Apply sticky-mask 's' to the reset-value 'v' and write to the address '= a'. + * RC-config space values and masks are LE. + * Method pnv_phb4_rc_config_read() returns BE, hence convert to LE. + * Compute new value in LE domain. + * New value computation using sticky-mask is in LE. + * Convert the computed value from LE to BE before writing back. + */ +#define RC_CONFIG_STICKY_RESET(a, v, s) \ + (pci_set_word(conf + (a), bswap32( \ + (bswap32(pci_get_word(conf + (a))) & (s)) | ((v) & ~(= s))))) + void pnv_phb4_cfg_core_reset(PCIDevice *d) { uint8_t *conf =3D d->config; @@ -560,14 +572,56 @@ void pnv_phb4_cfg_core_reset(PCIDevice *d) pci_set_long(conf + P16_ECAP, 0x22410026); pci_set_long(conf + P32_ECAP, 0x1002A); pci_set_long(conf + P32_CAP, 0x103); + + /* Sticky reset */ + RC_CONFIG_STICKY_RESET(exp_offset + PCI_EXP_LNKCTL2, + PCI_EXP_LNKCTL2_TLS_32_0GT, 0xFE= FFBF); + RC_CONFIG_STICKY_RESET(PHB_AER_UERR, 0, 0x1FF030); + RC_CONFIG_STICKY_RESET(PHB_AER_UERR_MASK, 0, 0x1FF030); + RC_CONFIG_STICKY_RESET(PHB_AER_CERR, 0, 0x11C1); + RC_CONFIG_STICKY_RESET(PHB_AER_ECAP + PCI_ERR_CAP, (PCI_ERR_CAP_ECRC_C= HKC + | PCI_ERR_CAP_ECRC_GENC), 0= x15F); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_1, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_2, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_3, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_HLOG_4, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_AER_RERR, 0, 0x7F); + RC_CONFIG_STICKY_RESET(PHB_AER_ESID, 0, 0xFFFFFFFF); + RC_CONFIG_STICKY_RESET(PHB_DLF_STAT, 0, 0x807FFFFF); + RC_CONFIG_STICKY_RESET(P16_STAT, 0, 0x1F); + RC_CONFIG_STICKY_RESET(P16_LDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P16_FRDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P16_SRDPM, 0, 0xFFFF); + RC_CONFIG_STICKY_RESET(P32_CTL, 0, 0x3); } =20 +/* Apply sticky-mask to the reset-value and write to the reg-address */ +#define STICKY_RST(addr, rst_val, sticky_mask) (phb->regs[addr >> 3] =3D \ + ((phb->regs[addr >> 3] & sticky_mask) | (rst_val & ~sticky_mas= k))) + static void pnv_phb4_pbl_core_reset(PnvPHB4 *phb) { - /* Zero all registers initially */ + /* + * Zero all registers initially, + * with sticky reset of certain registers. + */ for (int i =3D PHB_PBL_CONTROL ; i <=3D PHB_PBL_ERR1_STATUS_MASK ; i += =3D 8) { - phb->regs[i >> 3] =3D 0x0; + switch (i) { + case PHB_PBL_ERR_STATUS: + break; + case PHB_PBL_ERR1_STATUS: + case PHB_PBL_ERR_LOG_0: + case PHB_PBL_ERR_LOG_1: + case PHB_PBL_ERR_STATUS_MASK: + case PHB_PBL_ERR1_STATUS_MASK: + STICKY_RST(i, 0, PPC_BITMASK(0, 63)); + break; + default: + phb->regs[i >> 3] =3D 0x0; + } } + STICKY_RST(PHB_PBL_ERR_STATUS, 0, \ + (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63))); =20 /* Set specific register values */ phb->regs[PHB_PBL_CONTROL >> 3] =3D 0xC009000000000000; @@ -701,6 +755,17 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, } break; =20 + /* + * Writing bits to a 1 in this register will inject the error correspo= nding + * to the bit that is written. The bits will automatically clear to 0 = after + * the error is injected. The corresponding bit in the Error Status Reg + * should also be set automatically when the error occurs. + */ + case PHB_PBL_ERR_INJECT: + phb->regs[PHB_PBL_ERR_STATUS >> 3] =3D phb->regs[off >> 3]; + phb->regs[off >> 3] =3D 0; + break; + /* Silent simple writes */ case PHB_ASN_CMPM: case PHB_CONFIG_ADDRESS: @@ -1621,11 +1686,65 @@ static PCIIOMMUOps pnv_phb4_iommu_ops =3D { .get_address_space =3D pnv_phb4_dma_iommu, }; =20 +static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); + STICKY_RST(PHB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_TXE_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_TXE_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_ARB_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_ARB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_MRG_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_MRG_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + + STICKY_RST(PHB_RXE_TCE_ERR_STATUS, 0, PPC_BITMASK(0, 35)); + STICKY_RST(PHB_RXE_TCE_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_RXE_TCE_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); +} + +static void pnv_phb4_pcie_stack_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_PCIE_CRESET, 0xE000000000000000, \ + (PHB_PCIE_CRESET_PERST_N | PHB_PCIE_CRESET_REFCLK_= N)); + STICKY_RST(PHB_PCIE_DLP_ERRLOG1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_PCIE_DLP_ERRLOG2, 0, PPC_BITMASK(0, 31)); + STICKY_RST(PHB_PCIE_DLP_ERR_STATUS, 0, PPC_BITMASK(0, 15)); +} + +static void pnv_phb4_regb_err_reg_reset(PnvPHB4 *phb) +{ + STICKY_RST(PHB_REGB_ERR_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR1_STATUS, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_LOG_0, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_LOG_1, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR_STATUS_MASK, 0, PPC_BITMASK(0, 63)); + STICKY_RST(PHB_REGB_ERR1_STATUS_MASK, 0, PPC_BITMASK(0, 63)); +} + static void pnv_phb4_reset(Object *obj, ResetType type) { PnvPHB4 *phb =3D PNV_PHB4(obj); =20 pnv_phb4_pbl_core_reset(phb); + pnv_phb4_err_reg_reset(phb); + pnv_phb4_pcie_stack_reg_reset(phb); + pnv_phb4_regb_err_reg_reset(phb); } =20 static void pnv_phb4_instance_init(Object *obj) diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_= phb4_regs.h index 6892e21cc9..df5e86d29a 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -344,17 +344,32 @@ #define PHB_RC_CONFIG_SIZE 0x800 =20 #define PHB_AER_ECAP 0x100 +#define PHB_AER_UERR 0x104 +#define PHB_AER_UERR_MASK 0x108 +#define PHB_AER_CERR 0x110 #define PHB_AER_CAPCTRL 0x118 +#define PHB_AER_HLOG_1 0x11C +#define PHB_AER_HLOG_2 0x120 +#define PHB_AER_HLOG_3 0x124 +#define PHB_AER_HLOG_4 0x128 +#define PHB_AER_RERR 0x130 +#define PHB_AER_ESID 0x134 #define PHB_SEC_ECAP 0x148 #define PHB_LMR_ECAP 0x1A0 #define PHB_LMR_CTLSTA_2 0x1AC #define PHB_LMR_CTLSTA_16 0x1E4 #define PHB_DLF_ECAP 0x1E8 #define PHB_DLF_CAP 0x1EC +#define PHB_DLF_STAT 0x1F0 #define P16_ECAP 0x1F4 +#define P16_STAT 0x200 +#define P16_LDPM 0x204 +#define P16_FRDPM 0x208 +#define P16_SRDPM 0x20C #define P32_ECAP 0x224 #define P32_CAP 0x228 - +#define P32_CTL 0x22C +#define P32_STAT 0x230 /* PHB4 REGB registers */ =20 /* PBL core */ @@ -388,8 +403,7 @@ #define PHB_PCIE_CRESET_PBL PPC_BIT(2) #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) - - +#define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) =20 diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 8cd6c1bc59..419f34987a 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -22,6 +22,19 @@ #define PNV_P10_CHIP_INDEX 3 #define PHB4_XSCOM 0x40084800ull =20 +/* + * Indirect XSCOM write: + * - Write 'Indirect Address Register' with register-offset to write. + * - Write 'Indirect Data Register' with the value. + */ +static void pnv_phb_xscom_write(QTestState *qts, const PnvChip *chip, + uint64_t scom, uint32_t indirect_addr, uint32_t indirect_data, + uint64_t reg, uint64_t val) +{ + qtest_writeq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_addr), r= eg); + qtest_writeq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_data), v= al); +} + /* * Indirect XSCOM read:: * - Write 'Indirect Address Register' with register-offset to read. @@ -35,6 +48,11 @@ static uint64_t pnv_phb_xscom_read(QTestState *qts, cons= t PnvChip *chip, return qtest_readq(qts, pnv_xscom_addr(chip, (scom >> 3) + indirect_da= ta)); } =20 +#define PHB4_XSCOM_WRITE(a, v) pnv_phb_xscom_write(qts, \ + &pnv_chips[PNV_P10_CHIP_INDEX], PHB4_XS= COM, \ + PHB_SCOM_HV_IND_ADDR, PHB_SCOM_HV_IND_D= ATA, \ + PPC_BIT(0) | (a), (v)) + #define PHB4_XSCOM_READ(a) pnv_phb_xscom_read(qts, \ &pnv_chips[PNV_P10_CHIP_INDEX], PHB4_XS= COM, \ PHB_SCOM_HV_IND_ADDR, PHB_SCOM_HV_IND_D= ATA, \ @@ -46,6 +64,26 @@ static void phb4_reset_test(QTestState *qts) g_assert_cmpuint(PHB4_XSCOM_READ(PHB_PBL_CONTROL), =3D=3D, 0xC00900000= 0000000); } =20 +/* Check sticky-reset */ +static void phb4_sticky_rst_test(QTestState *qts) +{ + uint64_t val; + + /* + * Sticky reset test of PHB_PBL_ERR_STATUS. + * + * Write all 1's to reg PHB_PBL_ERR_INJECT. + * Updated value will be copied to reg PHB_PBL_ERR_STATUS. + * + * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESE= T. + * Verify the sticky bits are still set. + */ + PHB4_XSCOM_WRITE(PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63)); + PHB4_XSCOM_WRITE(PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/ + val =3D PHB4_XSCOM_READ(PHB_PBL_ERR_STATUS); + g_assert_cmpuint(val, =3D=3D, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63)= )); +} + static void phb4_tests(void) { QTestState *qts =3D NULL; @@ -55,6 +93,9 @@ static void phb4_tests(void) /* Check reset value of a register */ phb4_reset_test(qts); =20 + /* Check sticky reset of a register */ + phb4_sticky_rst_test(qts); + qtest_quit(qts); } =20 --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1772691054; cv=none; d=zohomail.com; s=zohoarc; b=RoTPoi2gg1BW+dMLMu18pm4yCOlOjOMuFWnXfTC+90TyBn86seSlHsXr7GueSk3BCf39ecbsZyR3SdItyYYPdoA82RpQvDc8a/x8ihaKPff4mLSdMj0QrREVCZHLuWqaf82HAf9hKLOziayKVeE2kbbfLNq3xIeMrNYrHhjngp4= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=X/gzmx EY/mB35RQ1q/lrGWnwR1OIXojG9ogPnPOI4ig=; b=PW4uFAoeSqnQKtf+xvkrZ8 b/JKSOF3VfjRhRXgKYem2MkmCklfpmM3kL6i5z8YHLmUjIbpYBKpLGL8+XJTd0IM nvzrGBzW1/UMOMp9oLU/YpvgFc8NCQzadV3rRbdm0p8sdVlIHylzGwALiSMkwnOR 11v73oCaxSafrSJE5RIr+wmsSWrlTo62OdjtYQC8hly/eWUT4THd/fKua647oqMc j/tJkk7hVZBo9LCZUO+PIMH6twzydBTeTaVXn/m6jKCHbiyfKXRcR2GhEQtigT3Z LHzGYEwc+hEiGkFXremUYQvcWLLNjYCGT9u3IEuuoPkW+21482StRh6yo0ZAiQ/A == From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v4 4/9] pnv/phb4: Implement read-only and write-only bits of registers Date: Thu, 5 Mar 2026 00:09:06 -0600 Message-ID: <20260305060923.3753402-5-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691056655139100 SW cannot write the read-only(RO) bits of a register and write-only(WO) bits of a register return 0 when read. Added ro_mask[] for each register that defines which bits in that register are RO. When writing to a register, the RO-bits are not updated. When reading a register, clear the WO bits and return the updated value. Tested the registers PHB_DMA_SYNC, PHB_PCIE_HOTPLUG_STATUS, PHB_PCIE_LMR, PHB_PCIE_DLP_TRWCTL, PHB_LEM_ERROR_AND_MASK and PHB_LEM_ERROR_OR_MASK by writing all 1's and reading back the value. The WO bits in these registers should read back as 0. Add .class_size in pnv_phb4_type_info. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: "Michael S. Tsirkin" --- v3: - Updates for coding guidelines. - Added class size for PnvPHB4Class. v2: New PnvPHB4Class to hold each register's RO mask. hw/pci-host/pnv_phb4.c | 80 ++++++++++++++++++++++++++--- include/hw/pci-host/pnv_phb4.h | 13 ++++- include/hw/pci-host/pnv_phb4_regs.h | 20 ++++++-- tests/qtest/pnv-phb4-test.c | 60 +++++++++++++++++++++- 4 files changed, 159 insertions(+), 14 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index b3f46f7fe1..7656c9cc19 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -707,6 +707,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, return; } =20 + /* Update 'val' according to the register's RO-mask */ + PnvPHB4Class *k =3D PNV_PHB4_GET_CLASS(phb); + + val =3D (phb->regs[off >> 3] & k->ro_mask[off >> 3]) | + (val & ~(k->ro_mask[off >> 3])); + /* Record whether it changed */ changed =3D phb->regs[off >> 3] !=3D val; =20 @@ -782,7 +788,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off= , uint64_t val, case PHB_TCE_TAG_ENABLE: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_DMARD_SYNC: + case PHB_DMA_SYNC: break; =20 /* Noise on anything else */ @@ -820,7 +826,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr = off, unsigned size) case PHB_VERSION: return PNV_PHB4_PEC_GET_CLASS(phb->pec)->version; =20 - /* Read-only */ + /* Read-only */ case PHB_PHB4_GEN_CAP: return 0xe4b8000000000000ull; case PHB_PHB4_TCE_CAP: @@ -830,18 +836,49 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwadd= r off, unsigned size) case PHB_PHB4_EEH_CAP: return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ul= l; =20 + /* Write-only, read will return zeros */ + case PHB_LEM_ERROR_AND_MASK: + case PHB_LEM_ERROR_OR_MASK: + return 0; + case PHB_PCIE_DLP_TRWCTL: + val &=3D ~PHB_PCIE_DLP_TRWCTL_WREN; + return val; /* IODA table accesses */ case PHB_IODA_DATA0: return pnv_phb4_ioda_read(phb); =20 + /* + * DMA sync: make it look like it's complete, + * clear write-only read/write start sync bits. + */ + case PHB_DMA_SYNC: + val =3D PHB_DMA_SYNC_RD_COMPLETE | + ~(PHB_DMA_SYNC_RD_START | PHB_DMA_SYNC_WR_START); + return val; + + /* + * PCI-E Stack registers + */ + case PHB_PCIE_SCR: + val |=3D PHB_PCIE_SCR_PLW_X16; /* RO bit */ + break; + /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: /* TODO: Do something sensible with speed ? */ - return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + val |=3D PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + return val; =20 - /* DMA read sync: make it look like it's complete */ - case PHB_DMARD_SYNC: - return PHB_DMARD_SYNC_COMPLETE; + case PHB_PCIE_HOTPLUG_STATUS: + /* Clear write-only bit */ + val &=3D ~PHB_PCIE_HPSTAT_RESAMPLE; + return val; + + /* Link Management Register */ + case PHB_PCIE_LMR: + /* These write-only bits always read as 0 */ + val &=3D ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + return val; =20 /* Silent simple reads */ case PHB_LSI_SOURCE_ID: @@ -1686,6 +1723,32 @@ static PCIIOMMUOps pnv_phb4_iommu_ops =3D { .get_address_space =3D pnv_phb4_dma_iommu, }; =20 +static void pnv_phb4_ro_mask_init(PnvPHB4 *phb) +{ + PnvPHB4Class *phb4c =3D PNV_PHB4_GET_CLASS(phb); + + /* + * Set register specific RO-masks + */ + + /* PBL - Error Injection Register (0x1910) */ + phb4c->ro_mask[PHB_PBL_ERR_INJECT >> 3] =3D + PPC_BITMASK(0, 23) | PPC_BITMASK(28, 35) | PPC_BIT(38) | PPC_BIT(4= 6) | + PPC_BITMASK(49, 51) | PPC_BITMASK(55, 63); + + /* Reserved bits[60:63] */ + phb4c->ro_mask[PHB_TXE_ERR_LEM_ENABLE >> 3] =3D + phb4c->ro_mask[PHB_TXE_ERR_AIB_FENCE_ENABLE >> 3] =3D PPC_BITMASK(60, = 63); + /* Reserved bits[36:63] */ + phb4c->ro_mask[PHB_RXE_TCE_ERR_LEM_ENABLE >> 3] =3D + phb4c->ro_mask[PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE >> 3] =3D PPC_BITMASK(= 36, 63); + /* Reserved bits[40:63] */ + phb4c->ro_mask[PHB_ERR_LEM_ENABLE >> 3] =3D + phb4c->ro_mask[PHB_ERR_AIB_FENCE_ENABLE >> 3] =3D PPC_BITMASK(40, 63); + + /* TODO: Add more RO-masks as regs are implemented in the model */ +} + static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) { STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); @@ -1745,6 +1808,7 @@ static void pnv_phb4_reset(Object *obj, ResetType typ= e) pnv_phb4_err_reg_reset(phb); pnv_phb4_pcie_stack_reg_reset(phb); pnv_phb4_regb_err_reg_reset(phb); + phb->regs[PHB_PCIE_CRESET >> 3] =3D 0xE000000000000000; } =20 static void pnv_phb4_instance_init(Object *obj) @@ -1755,6 +1819,9 @@ static void pnv_phb4_instance_init(Object *obj) =20 /* XIVE interrupt source object */ object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); + + /* Initialize RO-mask of registers */ + pnv_phb4_ro_mask_init(phb); } =20 void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *phb) @@ -1934,6 +2001,7 @@ static const TypeInfo pnv_phb4_type_info =3D { .parent =3D TYPE_DEVICE, .instance_init =3D pnv_phb4_instance_init, .instance_size =3D sizeof(PnvPHB4), + .class_size =3D sizeof(PnvPHB4Class), .class_init =3D pnv_phb4_class_init, .interfaces =3D (const InterfaceInfo[]) { { TYPE_XIVE_NOTIFIER }, diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 47a5c3edf5..bea0684724 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -19,7 +19,7 @@ =20 =20 #define TYPE_PNV_PHB4 "pnv-phb4" -OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) +OBJECT_DECLARE_TYPE(PnvPHB4, PnvPHB4Class, PNV_PHB4) =20 typedef struct PnvPhb4PecStack PnvPhb4PecStack; =20 @@ -156,6 +156,17 @@ struct PnvPHB4 { QLIST_HEAD(, PnvPhb4DMASpace) dma_spaces; }; =20 +typedef struct PnvPHB4Class { + DeviceClass parent_class; + + /* + * Read-only bitmask for registers + * Bit value: 1 =3D> RO bit + * 0 =3D> RW bit + */ + uint64_t ro_mask[PNV_PHB4_NUM_REGS]; +} PnvPHB4Class; + void pnv_phb4_pic_print_info(PnvPHB4 *phb, GString *buf); int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index); PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp); diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_= phb4_regs.h index df5e86d29a..dfd0e01d1e 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -180,9 +180,11 @@ #define PHB_M64_AOMASK 0x1d0 #define PHB_M64_UPPER_BITS 0x1f0 #define PHB_NXLATE_PREFIX 0x1f8 -#define PHB_DMARD_SYNC 0x200 -#define PHB_DMARD_SYNC_START PPC_BIT(0) -#define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) +#define PHB_DMA_SYNC 0x200 +#define PHB_DMA_SYNC_RD_START PPC_BIT(0) +#define PHB_DMA_SYNC_RD_COMPLETE PPC_BIT(1) +#define PHB_DMA_SYNC_WR_START PPC_BIT(2) +#define PHB_DMA_SYNC_WR_COMPLETE PPC_BIT(3) #define PHB_RTC_INVALIDATE 0x208 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) @@ -370,6 +372,7 @@ #define P32_CAP 0x228 #define P32_CTL 0x22C #define P32_STAT 0x230 + /* PHB4 REGB registers */ =20 /* PBL core */ @@ -395,8 +398,8 @@ #define PHB_PCIE_SCR 0x1A00 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32, 35) +#define PHB_PCIE_SCR_PLW_X16 PPC_BIT(41) /* x16 */ #define PHB_PCIE_BNR 0x1A08 - #define PHB_PCIE_CRESET 0x1A10 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) @@ -405,7 +408,14 @@ #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 +#define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3) +#define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9) #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) +#define PHB_PCIE_HPSTAT_LINKACTIVE PPC_BIT(12) +#define PHB_PCIE_LMR 0x1A30 +#define PHB_PCIE_LMR_CHANGELW PPC_BIT(0) +#define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1) +#define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8) =20 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) @@ -433,7 +443,7 @@ =20 #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) - +#define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1) #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 419f34987a..2078fab9a9 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -73,7 +73,8 @@ static void phb4_sticky_rst_test(QTestState *qts) * Sticky reset test of PHB_PBL_ERR_STATUS. * * Write all 1's to reg PHB_PBL_ERR_INJECT. - * Updated value will be copied to reg PHB_PBL_ERR_STATUS. + * RO-only bits will not be written and + * updated value will be copied to reg PHB_PBL_ERR_STATUS. * * Reset PBL core by setting PHB_PCIE_CRESET_PBL in reg PHB_PCIE_CRESE= T. * Verify the sticky bits are still set. @@ -81,7 +82,59 @@ static void phb4_sticky_rst_test(QTestState *qts) PHB4_XSCOM_WRITE(PHB_PBL_ERR_INJECT, PPC_BITMASK(0, 63)); PHB4_XSCOM_WRITE(PHB_PCIE_CRESET, PHB_PCIE_CRESET_PBL); /*Reset*/ val =3D PHB4_XSCOM_READ(PHB_PBL_ERR_STATUS); - g_assert_cmpuint(val, =3D=3D, (PPC_BITMASK(0, 9) | PPC_BITMASK(12, 63)= )); + g_assert_cmpuint(val, =3D=3D, 0xF00DFD8E00); +} + +/* Check that write-only bits/regs return 0 when read */ +static void phb4_writeonly_read_test(QTestState *qts) +{ + uint64_t val; + + /* + * Set all bits of PHB_DMA_SYNC, + * bits 0 and 2 are write-only and should be read as 0. + */ + PHB4_XSCOM_WRITE(PHB_DMA_SYNC, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_DMA_SYNC); + g_assert_cmpuint(val & PPC_BIT(0), =3D=3D, 0x0); + g_assert_cmpuint(val & PPC_BIT(2), =3D=3D, 0x0); + + /* + * Set all bits of PHB_PCIE_HOTPLUG_STATUS, + * bit 9 is write-only and should be read as 0. + */ + PHB4_XSCOM_WRITE(PHB_PCIE_HOTPLUG_STATUS, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_PCIE_HOTPLUG_STATUS); + g_assert_cmpuint(val & PPC_BIT(9), =3D=3D, 0x0); + + /* + * Set all bits of PHB_PCIE_LMR, + * bits 0 and 1 are write-only and should be read as 0. + */ + PHB4_XSCOM_WRITE(PHB_PCIE_LMR, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_PCIE_LMR); + g_assert_cmpuint(val & PPC_BIT(0), =3D=3D, 0x0); + g_assert_cmpuint(val & PPC_BIT(1), =3D=3D, 0x0); + + /* + * Set all bits of PHB_PCIE_DLP_TRWCTL, + * write-only bit-1 should be read as 0. + */ + PHB4_XSCOM_WRITE(PHB_PCIE_DLP_TRWCTL, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_PCIE_DLP_TRWCTL); + g_assert_cmpuint(val & PPC_BIT(1), =3D=3D, 0x0); + + /* + * Set all bits of PHB_LEM_ERROR_AND_MASK, PHB_LEM_ERROR_OR_MASK, + * both regs are write-only and should be read as 0. + */ + PHB4_XSCOM_WRITE(PHB_LEM_ERROR_AND_MASK, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_LEM_ERROR_AND_MASK); + g_assert_cmpuint(val, =3D=3D, 0x0); + + PHB4_XSCOM_WRITE(PHB_LEM_ERROR_OR_MASK, PPC_BITMASK(0, 63)); + val =3D PHB4_XSCOM_READ(PHB_LEM_ERROR_OR_MASK); + g_assert_cmpuint(val, =3D=3D, 0x0); } =20 static void phb4_tests(void) @@ -96,6 +149,9 @@ static void phb4_tests(void) /* Check sticky reset of a register */ phb4_sticky_rst_test(qts); =20 + /* Check write-only logic */ + phb4_writeonly_read_test(qts); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691056631158500 Implement write-1-to-clear and write-X-to-clear logic. Update registers with silent simple read and write. Return all 1's when an unimplemented/reserved register is read. Test that reading address 0x0 returns all 1's (i.e. -1). Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater --- v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 190 ++++++++++++++++++++++------ include/hw/pci-host/pnv_phb4_regs.h | 11 +- tests/qtest/pnv-phb4-test.c | 9 ++ 3 files changed, 169 insertions(+), 41 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 7656c9cc19..25539b7c32 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -655,8 +655,41 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, return; } =20 - /* Handle masking */ + /* Handle RO, W1C, WxC and masking */ switch (off) { + /* W1C: Write-1-to-Clear registers */ + case PHB_TXE_ERR_STATUS: + case PHB_RXE_ARB_ERR_STATUS: + case PHB_RXE_MRG_ERR_STATUS: + case PHB_RXE_TCE_ERR_STATUS: + case PHB_ERR_STATUS: + case PHB_REGB_ERR_STATUS: + case PHB_PCIE_DLP_ERRLOG1: + case PHB_PCIE_DLP_ERRLOG2: + case PHB_PCIE_DLP_ERR_STATUS: + case PHB_PBL_ERR_STATUS: + phb->regs[off >> 3] &=3D ~val; + return; + + /* WxC: Clear register on any write */ + case PHB_PBL_ERR1_STATUS: + case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR_LOG_1: + case PHB_REGB_ERR1_STATUS: + case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR_LOG_1: + case PHB_TXE_ERR1_STATUS: + case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR_LOG_1: + case PHB_RXE_ARB_ERR1_STATUS: + case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR_LOG_1: + case PHB_RXE_MRG_ERR1_STATUS: + case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR_LOG_1: + case PHB_RXE_TCE_ERR1_STATUS: + case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR_LOG_1: + case PHB_ERR1_STATUS: + case PHB_ERR_LOG_0 ... PHB_ERR_LOG_1: + phb->regs[off >> 3] =3D 0; + return; + + /* Write value updated by masks */ case PHB_LSI_SOURCE_ID: val &=3D PHB_LSI_SRC_ID; break; @@ -695,7 +728,6 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off= , uint64_t val, case PHB_LEM_WOF: val =3D 0; break; - /* TODO: More regs ..., maybe create a table with masks... */ =20 /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: @@ -704,6 +736,12 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, case PHB_PHB4_TCE_CAP: case PHB_PHB4_IRQ_CAP: case PHB_PHB4_EEH_CAP: + case PHB_VERSION: + case PHB_DMA_CHAN_STATUS: + case PHB_TCE_TAG_STATUS: + case PHB_PBL_BUF_STATUS: + case PHB_PCIE_BNR: + case PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_= 15: return; } =20 @@ -726,6 +764,7 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off= , uint64_t val, pnv_phb4_update_all_msi_regions(phb); } break; + case PHB_M32_START_ADDR: case PHB_M64_UPPER_BITS: if (changed) { @@ -773,27 +812,63 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr o= ff, uint64_t val, break; =20 /* Silent simple writes */ - case PHB_ASN_CMPM: - case PHB_CONFIG_ADDRESS: - case PHB_IODA_ADDR: - case PHB_TCE_KILL: - case PHB_TCE_SPEC_CTL: - case PHB_PEST_BAR: - case PHB_PELTV_BAR: + /* PHB Fundamental register set A */ + case PHB_CONFIG_DATA ... PHB_LOCK1: case PHB_RTT_BAR: - case PHB_LEM_FIR_ACCUM: - case PHB_LEM_ERROR_MASK: - case PHB_LEM_ACTION0: - case PHB_LEM_ACTION1: - case PHB_TCE_TAG_ENABLE: + case PHB_PELTV_BAR: + case PHB_PEST_BAR: + case PHB_CAPI_CMPM ... PHB_M64_AOMASK: + case PHB_NXLATE_PREFIX ... PHB_DMA_SYNC: + case PHB_TCE_KILL ... PHB_IODA_ADDR: + case PHB_PAPR_ERR_INJ_CTL ... PHB_PAPR_ERR_INJ_MASK: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_DMA_SYNC: - break; + /* Fundamental register set B */ + case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R: + /* FIR & Error registers */ + case PHB_LEM_FIR_ACCUM: + case PHB_LEM_ERROR_MASK: + case PHB_LEM_ACTION0 ... PHB_LEM_WOF: + case PHB_ERR_INJECT ... PHB_ERR_AIB_FENCE_ENABLE: + case PHB_ERR_STATUS_MASK ... PHB_ERR1_STATUS_MASK: + case PHB_TXE_ERR_INJECT ... PHB_TXE_ERR_AIB_FENCE_ENABLE: + case PHB_TXE_ERR_STATUS_MASK ... PHB_TXE_ERR1_STATUS_MASK: + case PHB_RXE_ARB_ERR_INJECT ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_ARB_ERR_STATUS_MASK ... PHB_RXE_ARB_ERR1_STATUS_MASK: + case PHB_RXE_MRG_ERR_INJECT ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_MRG_ERR_STATUS_MASK ... PHB_RXE_MRG_ERR1_STATUS_MASK: + case PHB_RXE_TCE_ERR_INJECT ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_TCE_ERR_STATUS_MASK ... PHB_RXE_TCE_ERR1_STATUS_MASK: + /* Performance monitor & Debug registers */ + case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1: + /* REGB Registers */ + /* PBL core */ + case PHB_PBL_CONTROL: + case PHB_PBL_TIMEOUT_CTRL: + case PHB_PBL_NPTAG_ENABLE: + case PHB_PBL_SYS_LINK_INIT: + case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE: + case PHB_PBL_ERR_STATUS_MASK ... PHB_PBL_ERR1_STATUS_MASK: + /* PCI-E stack */ + case PHB_PCIE_SCR: + case PHB_PCIE_DLP_STR ... PHB_PCIE_HOTPLUG_STATUS: + case PHB_PCIE_LMR ... PHB_PCIE_DLP_LSR: + case PHB_PCIE_DLP_RXMGN: + case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_TRCRDDATA: + case PHB_PCIE_DLP_ERR_COUNTERS: + case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23: + case PHB_PCIE_TRACE_CTRL: + case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_EQ_CTL: + /* Error registers */ + case PHB_REGB_ERR_INJECT: + case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE: + case PHB_REGB_ERR_STATUS_MASK ... PHB_REGB_ERR1_STATUS_MASK: + break; =20 /* Noise on anything else */ default: - qemu_log_mask(LOG_UNIMP, "phb4: reg_write 0x%"PRIx64"=3D%"PRIx64"\= n", + qemu_log_mask(LOG_UNIMP, + "phb4: unimplemented reg_write 0x%"PRIx64"=3D%"PRIx6= 4"\n", off, val); } } @@ -881,36 +956,75 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwadd= r off, unsigned size) return val; =20 /* Silent simple reads */ + /* PHB Fundamental register set A */ case PHB_LSI_SOURCE_ID: + case PHB_DMA_CHAN_STATUS: case PHB_CPU_LOADSTORE_STATUS: - case PHB_ASN_CMPM: + case PHB_CONFIG_DATA ... PHB_LOCK1: case PHB_PHB4_CONFIG: + case PHB_RTT_BAR: + case PHB_PELTV_BAR: case PHB_M32_START_ADDR: - case PHB_CONFIG_ADDRESS: - case PHB_IODA_ADDR: - case PHB_RTC_INVALIDATE: - case PHB_TCE_KILL: - case PHB_TCE_SPEC_CTL: case PHB_PEST_BAR: - case PHB_PELTV_BAR: - case PHB_RTT_BAR: + case PHB_CAPI_CMPM: + case PHB_M64_AOMASK: case PHB_M64_UPPER_BITS: - case PHB_CTRLR: - case PHB_LEM_FIR_ACCUM: - case PHB_LEM_ERROR_MASK: - case PHB_LEM_ACTION0: - case PHB_LEM_ACTION1: - case PHB_TCE_TAG_ENABLE: + case PHB_NXLATE_PREFIX: + case PHB_RTC_INVALIDATE ... PHB_IODA_ADDR: + case PHB_PAPR_ERR_INJ_CTL ... PHB_ETU_ERR_SUMMARY: case PHB_INT_NOTIFY_ADDR: case PHB_INT_NOTIFY_INDEX: - case PHB_Q_DMA_R: - case PHB_ETU_ERR_SUMMARY: - break; - - /* Noise on anything else */ + /* Fundamental register set B */ + case PHB_CTRLR: + case PHB_AIB_FENCE_CTRL ... PHB_Q_DMA_R: + case PHB_TCE_TAG_STATUS: + /* FIR & Error registers */ + case PHB_LEM_FIR_ACCUM ... PHB_LEM_ERROR_MASK: + case PHB_LEM_ACTION0 ... PHB_LEM_WOF: + case PHB_ERR_STATUS ... PHB_ERR_AIB_FENCE_ENABLE: + case PHB_ERR_LOG_0 ... PHB_ERR1_STATUS_MASK: + case PHB_TXE_ERR_STATUS ... PHB_TXE_ERR_AIB_FENCE_ENABLE: + case PHB_TXE_ERR_LOG_0 ... PHB_TXE_ERR1_STATUS_MASK: + case PHB_RXE_ARB_ERR_STATUS ... PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_ARB_ERR_LOG_0 ... PHB_RXE_ARB_ERR1_STATUS_MASK: + case PHB_RXE_MRG_ERR_STATUS ... PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_MRG_ERR_LOG_0 ... PHB_RXE_MRG_ERR1_STATUS_MASK: + case PHB_RXE_TCE_ERR_STATUS ... PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE: + case PHB_RXE_TCE_ERR_LOG_0 ... PHB_RXE_TCE_ERR1_STATUS_MASK: + /* Performance monitor & Debug registers */ + case PHB_TRACE_CONTROL ... PHB_PERFMON_CTR1: + /* REGB Registers */ + /* PBL core */ + case PHB_PBL_CONTROL: + case PHB_PBL_TIMEOUT_CTRL: + case PHB_PBL_NPTAG_ENABLE: + case PHB_PBL_SYS_LINK_INIT: + case PHB_PBL_BUF_STATUS: + case PHB_PBL_ERR_STATUS ... PHB_PBL_ERR_INJECT: + case PHB_PBL_ERR_INF_ENABLE ... PHB_PBL_ERR_FAT_ENABLE: + case PHB_PBL_ERR_LOG_0 ... PHB_PBL_ERR1_STATUS_MASK: + /* PCI-E stack */ + case PHB_PCIE_BNR ... PHB_PCIE_DLP_STR: + case PHB_PCIE_DLP_LANE_PWR: + case PHB_PCIE_DLP_LSR: + case PHB_PCIE_DLP_RXMGN: + case PHB_PCIE_DLP_LANEZEROCTL ... PHB_PCIE_DLP_CTL: + case PHB_PCIE_DLP_TRCRDDATA: + case PHB_PCIE_DLP_ERRLOG1 ... PHB_PCIE_DLP_ERR_COUNTERS: + case PHB_PCIE_DLP_EIC ... PHB_PCIE_LANE_EQ_CNTL23: + case PHB_PCIE_TRACE_CTRL: + case PHB_PCIE_MISC_STRAP ... PHB_PCIE_PHY_RXEQ_STAT_G5_12_15: + /* Error registers */ + case PHB_REGB_ERR_STATUS ... PHB_REGB_ERR_INJECT: + case PHB_REGB_ERR_INF_ENABLE ... PHB_REGB_ERR_FAT_ENABLE: + case PHB_REGB_ERR_LOG_0 ... PHB_REGB_ERR1_STATUS_MASK: + break; + + /* Noise on unimplemented read, return all 1's */ default: - qemu_log_mask(LOG_UNIMP, "phb4: reg_read 0x%"PRIx64"=3D%"PRIx64"\n= ", - off, val); + qemu_log_mask(LOG_UNIMP, "phb4: unimplemented reg_read 0x%"PRIx64"= \n", + off); + val =3D ~0ull; } return val; } diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_= phb4_regs.h index dfd0e01d1e..c1d5a83271 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -407,6 +407,7 @@ #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) #define PHB_PCIE_CRESET_REFCLK_N PPC_BIT(8) +#define PHB_PCIE_DLP_STR 0x1A18 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 #define PHB_PCIE_HPSTAT_SIMDIAG PPC_BIT(3) #define PHB_PCIE_HPSTAT_RESAMPLE PPC_BIT(9) @@ -417,6 +418,7 @@ #define PHB_PCIE_LMR_RETRAINLINK PPC_BIT(1) #define PHB_PCIE_LMR_LINKACTIVE PPC_BIT(8) =20 +#define PHB_PCIE_DLP_LANE_PWR 0x1A38 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30, 35) #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36, 39) @@ -436,18 +438,21 @@ #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) - +#define PHB_PCIE_DLP_LSR 0x1A48 +#define PHB_PCIE_DLP_RXMGN 0x1A50 +#define PHB_PCIE_DLP_LANEZEROCTL 0x1A70 #define PHB_PCIE_DLP_CTL 0x1A78 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) - #define PHB_PCIE_DLP_TRWCTL 0x1A80 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) #define PHB_PCIE_DLP_TRWCTL_WREN PPC_BIT(1) +#define PHB_PCIE_DLP_TRCRDDATA 0x1A88 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 +#define PHB_PCIE_DLP_EIC 0x1AC8 =20 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 @@ -459,6 +464,7 @@ #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ #define PHB_PCIE_TRACE_CTRL 0x1B20 #define PHB_PCIE_MISC_STRAP 0x1B30 +#define PHB_PCIE_PHY_EQ_CTL 0x1B38 #define PHB_PCIE_PHY_RXEQ_STAT_G3_00_03 0x1B40 #define PHB_PCIE_PHY_RXEQ_STAT_G5_12_15 0x1B98 =20 @@ -592,5 +598,4 @@ =20 #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3, 63) =20 - #endif /* PCI_HOST_PNV_PHB4_REGS_H */ diff --git a/tests/qtest/pnv-phb4-test.c b/tests/qtest/pnv-phb4-test.c index 2078fab9a9..9ccb75cd5a 100644 --- a/tests/qtest/pnv-phb4-test.c +++ b/tests/qtest/pnv-phb4-test.c @@ -137,6 +137,12 @@ static void phb4_writeonly_read_test(QTestState *qts) g_assert_cmpuint(val, =3D=3D, 0x0); } =20 +/* Check that reading an unimplemented address 0x0 returns -1 */ +static void phb4_unimplemented_read_test(QTestState *qts) +{ + g_assert_cmpint(PHB4_XSCOM_READ(0x0), =3D=3D, -1); +} + static void phb4_tests(void) { QTestState *qts =3D NULL; @@ -152,6 +158,9 @@ static void phb4_tests(void) /* Check write-only logic */ phb4_writeonly_read_test(qts); =20 + /* Check unimplemented register read */ + phb4_unimplemented_read_test(qts); + qtest_quit(qts); } =20 --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1772691054; cv=none; d=zohomail.com; s=zohoarc; b=SvdjWhoEcLCASHq8MrAOqYxZmxF4zKmNpDInVJHBDylQ9fMD12EqjAOLGuDYBR2i4bDG6hyF20R74S++/nba29yxArNVKuVdisN+IN5AJH3UBBka17XVg8/JPwJkj7zAF1PhGXpdotD63uS4bS9UPP2YFJxkpyC4LUVvxSev1/w= ARC-Message-Signature: i=1; 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a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=rlVmvqf7TTqxevRDS H6/7XkYiRxu/TeAU/Po896My0E=; b=n5Y2jy/hIrfmob7+idzlFVZY7IiHcRj59 4eHoZqGjOXDgDRKpAsKYWwevCU9SbNBMZ+t7d3DHOFpW4iY2oi7KKqpQtYA0jBkv jJV6jXzEdtjmSaSz1En4vwk87OTjEhW2I9milXAQD8ZzRCoXTArwV804wS7Ag5ox v0aBVzkqL7mPP48fuOBJh2vTkR9SSKcMUVGT8pAs+jTj0BxJzjD01ri2xJhE/qQK KbLWrr8Tgr5YYnTZIgNV4i00hPYwQtVogOd+CvWv4bbNw2aHC3Q8wqT+VXrC4IEI R1/Gb7JJwGlVG4y4qWLNJGrYIwbB86YZkhlx60QDYsk/bszuG6wuA== From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v4 6/9] pnv/phb4: Set link-active status in HPSTAT and LMR registers Date: Thu, 5 Mar 2026 00:09:08 -0600 Message-ID: <20260305060923.3753402-7-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMzA1MDA0NiBTYWx0ZWRfX72z8yGDF745i MbKlAN6jFvXeWI2G1dzXSDA73fs1qu1SwP79WoFemsucI5vaWpHbJ7mgWLGKXvECazxlBM8eqKd BJSQlz8sGecBeJxxnLZb4vUcPg3BKfkQQ+2Wz3UMO1AKhBcOt05itLeJO9/WCztU4g7Pg1ygJeh zkEUKmsLeRMGRF2wHY9prshNPFQEDbj2DEGpAS5D795wChOla4YPgtQnH0ehQfLR8m+8wjuHkXy cgUarPs5Ml5yWAFS3qvoAX5WojCitdqeXUm9EUFmCleaw5Z/rqV2z2rK8zzeAIb5IEEPHzd1RET JoCDGjMLk7F+6PqCEyDiqXQEzVUiR154mJ3ppBFQlIogZYcvetmqORmnazqMILVicnOlZHZOPEl 69tDDxY9HoH9Bl8L4inm5y0ayl3hMLmw+Inwl3CiYkPx9GhEU3xAkqqngTjC/A4gLeBxab9wBsh ByCr8F2GRdlqtpcadvQ== X-Proofpoint-ORIG-GUID: iUYdCPQtGKFkpqkqBQO7kWf8UVXkRrT7 X-Proofpoint-GUID: 4XjDsMEv8Lr4vB0NC9uJcq3L4-JpPhY8 X-Authority-Analysis: v=2.4 cv=AobjHe9P c=1 sm=1 tr=0 ts=69a91e24 cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=20KFwNOVAAAA:8 a=SX2aUA2rIF85faSKF8YA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-03-05_01,2026-03-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 malwarescore=0 spamscore=0 clxscore=1015 suspectscore=0 adultscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2603050046 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Config-read the link-status register in the PCI-E macro, Depending on the link-active bit, set the link-active status in the HOTPLUG_STATUS and LINK_MANAGEMENT registers Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg after config-reading the slot-status in the PCI-E macro. Signed-off-by: Saif Abrar Reviewed-by: Michael S. Tsirkin --- v4: Variables declaration moved to the top of the method pnv_phb4_reg_read(= ). v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 59 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 25539b7c32..c35f632e64 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -511,6 +511,20 @@ static uint32_t get_exp_offset(PCIDevice *pdev) return rpc->exp_offset; } =20 +/* + * Config-read the link-status register in the PCI-E macro, + * convert to LE and check the link-active bit. + */ +static uint32_t is_link_active(PnvPHB4 *phb) +{ + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); + PCIDevice *pdev =3D pci_find_device(pci->bus, 0, 0); + uint32_t exp_offset =3D get_exp_offset(pdev); + + return (bswap32(pnv_phb4_rc_config_read(phb, exp_offset + PCI_EXP_LNKS= TA, 4) + ) & PCI_EXP_LNKSTA_DLLLA); +} + /* * Apply sticky-mask 's' to the reset-value 'v' and write to the address '= a'. * RC-config space values and masks are LE. @@ -729,6 +743,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, val =3D 0; break; =20 + case PHB_PCIE_HOTPLUG_STATUS: + /* For normal operations, Simspeed diagnostic bit is always zero */ + val &=3D PHB_PCIE_HPSTAT_SIMDIAG; + break; + /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: case PHB_ETU_ERR_SUMMARY: @@ -876,6 +895,10 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr of= f, uint64_t val, static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) { PnvPHB4 *phb =3D PNV_PHB4(opaque); + /* Get the PCI-E capability offset from the root-port */ + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); + PCIDevice *pdev =3D pci_find_device(pci->bus, 0, 0); + uint32_t exp_base =3D get_exp_offset(pdev); uint64_t val; =20 if ((off & 0xfffc) =3D=3D PHB_CONFIG_DATA) { @@ -944,8 +967,37 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr= off, unsigned size) val |=3D PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; return val; =20 + /* + * Read PCI-E registers and set status for: + * - Card present (active low bit 10) + * - Link active (bit 12) + */ case PHB_PCIE_HOTPLUG_STATUS: - /* Clear write-only bit */ + /* + * Presence-status bit hpi_present_n is active-low, with reset val= ue 1. + * Start by setting this bit to 1, indicating the card is not pres= ent. + * Then check the PCI-E register and clear the bit if card is pres= ent. + */ + val |=3D PHB_PCIE_HPSTAT_PRESENCE; + + /* + * Config-read the PCI-E macro register for slot-status. + * Method for config-read converts to BE value. + * To check actual bit in the PCI-E register, + * convert the value back to LE using bswap32(). + * Clear the Presence-status active low bit. + */ + if (bswap32(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA= , 4)) + & PCI_EXP_SLTSTA_PDS) { + val &=3D ~PHB_PCIE_HPSTAT_PRESENCE; + } + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |=3D PHB_PCIE_HPSTAT_LINKACTIVE; + } + + /* Clear write-only resample-bit */ val &=3D ~PHB_PCIE_HPSTAT_RESAMPLE; return val; =20 @@ -953,6 +1005,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwadd= r off, unsigned size) case PHB_PCIE_LMR: /* These write-only bits always read as 0 */ val &=3D ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |=3D PHB_PCIE_LMR_LINKACTIVE; + } return val; =20 /* Silent simple reads */ --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 5 Mar 2026 06:09:38 +0000 (GMT) Received: from smtpav02.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 678F758058; Thu, 5 Mar 2026 06:09:37 +0000 (GMT) Received: from gfwr526.rchland.ibm.com (unknown [9.10.239.119]) by smtpav02.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 5 Mar 2026 06:09:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=b+XhsK vRYPW3JE1OvwlBIyYvEPl0zOAy2CVX0NwTbwk=; b=eWjfHK4xbHmCyhuftd5XLi mzVh1VkSeEWeniEyAqPbQmSWHDswWrloZmryPfZZDCD/SBIYZMF46EmC+IZHxjuG tgQAC9O/26WY6ZlqgtePfpV0o/aSDBLnEg0TpRJWKrYx1W3rHAqWB6+xythrYjA5 N1ifmFoXYhlOK+NAn8SjGxERmgWpyUbJxRcLiiWaJNpgudhnQLiPgEJAix5z+X8V lCWs8Wdbd0F2A3fD2U+mlp81w9t1lelDMJ+J4/69/hJTHdhkzVvlEuPp6+wTDNE6 /OJtrCPGv7yqRjPDuqH9Gq6CdevGPZOcEZr7BaQpyBfTTFWkXCBV7wU6zPlePqQw == From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v4 7/9] pnv/phb4: Set link speed and width in the DLP training control register Date: Thu, 5 Mar 2026 00:09:09 -0600 Message-ID: <20260305060923.3753402-8-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691063181158500 Get the current link-status from PCIE macro. Extract link-speed and link-width from the link-status and set in the DLP training control (PCIE_DLP_TCR) register. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Michael S. Tsirkin --- v4: Variables declaration moved to the top of the method pnv_phb4_reg_read(= ). v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index c35f632e64..a6fa578e85 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -900,6 +900,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr = off, unsigned size) PCIDevice *pdev =3D pci_find_device(pci->bus, 0, 0); uint32_t exp_base =3D get_exp_offset(pdev); uint64_t val; + uint32_t v, lnkstatus; =20 if ((off & 0xfffc) =3D=3D PHB_CONFIG_DATA) { return pnv_phb4_config_read(phb, off & 0x3, size); @@ -961,10 +962,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwadd= r off, unsigned size) val |=3D PHB_PCIE_SCR_PLW_X16; /* RO bit */ break; =20 - /* Link training always appears trained */ case PHB_PCIE_DLP_TRAIN_CTL: - /* TODO: Do something sensible with speed ? */ + /* Get the current link-status from PCIE */ + lnkstatus =3D bswap32(pnv_phb4_rc_config_read(phb, + exp_base + PCI_EXP_LNKSTA, 4)); + + /* Extract link-speed from the link-status */ + v =3D lnkstatus & PCI_EXP_LNKSTA_CLS; + + /* Link training always appears trained */ val |=3D PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; + + /* Set the current link-speed at the LINK_SPEED position */ + val =3D SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v); + + /* + * Extract link-width from the link-status, + * after shifting the required bitfields. + */ + v =3D (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT; + /* Set the current link-width at the LINK_WIDTH position */ + val =3D SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v); return val; =20 /* --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; 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Thu, 5 Mar 2026 06:09:38 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=YCYnAE f4gdUyivqaZyTHoDfMItTr8g3o7+n4vdKNlP0=; b=VeZpJTLj2nnuQXb3TLc411 jckhjpPKtktNlGeqs6xhVJRpwMqNpa9JXCzE7XZTOaE3WmVFfIDXUtw1R+QEvXQk MtZYVGtUpYms4A1vfW7nHi3bIdrO4R3tyF1t3JmSa4lrklS47ushQaDZnId5duHC PcAPRXSOD4LlFsVUYQRP80bhukqERoy3qq0tTmepe3UgxYFUks2hI47vGLjbGYtY RbKgWRZ1tumkoJZ0OF7kOPWM4708i7ZhWojruZK1cuoS/20OjlYi6A7oHLOohta8 nbuoDe1HSAkMD5dTaCVCU9PJutnBB8ju6kQ3crRbOnmnLNepzVXPvYRJN06MnEZg == From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, danielhb413@gmail.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH v4 8/9] pnv/phb4: Implement IODA PCT table Date: Thu, 5 Mar 2026 00:09:10 -0600 Message-ID: <20260305060923.3753402-9-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> References: <20260210134110.1515322-1-saif.abrar@linux.vnet.ibm.com> <20260305060923.3753402-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691084728139100 IODA PCT table (#3) is implemented without any functionality, being a debug table. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater --- v3: Updates for coding guidelines. hw/pci-host/pnv_phb4.c | 6 ++++++ include/hw/pci-host/pnv_phb4.h | 2 ++ include/hw/pci-host/pnv_phb4_regs.h | 1 + 3 files changed, 9 insertions(+) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index a6fa578e85..254bbe4089 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -264,6 +264,10 @@ static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, mask =3D phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> = 1); mask -=3D 1; break; + case IODA3_TBL_PCT: + tptr =3D phb->ioda_PCT; + mask =3D 7; + break; case IODA3_TBL_RCAM: mask =3D phb->big_phb ? 127 : 63; break; @@ -362,6 +366,8 @@ static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t = val) /* Handle side effects */ switch (table) { case IODA3_TBL_LIST: + case IODA3_TBL_PCT: + /* No action for debug tables */ break; case IODA3_TBL_MIST: { /* Special mask for MIST partial write */ diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index bea0684724..6bb75edeef 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -65,6 +65,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4RootBus, PNV_PHB4_ROOT_= BUS) #define PNV_PHB4_MAX_LSIs 8 #define PNV_PHB4_MAX_INTs 4096 #define PNV_PHB4_MAX_MIST (PNV_PHB4_MAX_INTs >> 2) +#define PNV_PHB4_MAX_PCT 128 #define PNV_PHB4_MAX_MMIO_WINDOWS 32 #define PNV_PHB4_MIN_MMIO_WINDOWS 16 #define PNV_PHB4_NUM_REGS (0x3000 >> 3) @@ -138,6 +139,7 @@ struct PnvPHB4 { /* On-chip IODA tables */ uint64_t ioda_LIST[PNV_PHB4_MAX_LSIs]; uint64_t ioda_MIST[PNV_PHB4_MAX_MIST]; + uint64_t ioda_PCT[PNV_PHB4_MAX_PCT]; uint64_t ioda_TVT[PNV_PHB4_MAX_TVEs]; uint64_t ioda_MBT[PNV_PHB4_MAX_MBEs]; uint64_t ioda_MDT[PNV_PHB4_MAX_PEs]; diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_= phb4_regs.h index c1d5a83271..e30adff7b2 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -486,6 +486,7 @@ =20 #define IODA3_TBL_LIST 1 #define IODA3_TBL_MIST 2 +#define IODA3_TBL_PCT 3 #define IODA3_TBL_RCAM 5 #define IODA3_TBL_MRT 6 #define IODA3_TBL_PESTA 7 --=20 2.47.3 From nobody Sat Apr 11 21:30:51 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.vnet.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1772691071; cv=none; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=148.163.156.1; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1772691074776139100 Add a method to reset the value of LSI Source-ID. Mask off LSI source-id based on number of interrupts in the big/small PHB. Signed-off-by: Saif Abrar Reviewed-by: C=C3=A9dric Le Goater --- v3: Updates for coding guidelines. v2: Introduced method pnv_phb4_xsrc_reset(). hw/pci-host/pnv_phb4.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 254bbe4089..5e885cb89d 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -490,6 +490,7 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) =20 lsi_base =3D GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3= ]); lsi_base <<=3D 3; + lsi_base &=3D (xsrc->nr_irqs - 1); =20 /* TODO: handle reset values of PHB_LSI_SRC_ID */ if (!lsi_base) { @@ -1944,6 +1945,12 @@ static void pnv_phb4_ro_mask_init(PnvPHB4 *phb) /* TODO: Add more RO-masks as regs are implemented in the model */ } =20 +static void pnv_phb4_xsrc_reset(PnvPHB4 *phb) +{ + phb->regs[PHB_LSI_SOURCE_ID >> 3] =3D PPC_BITMASK(4, 12); + pnv_phb4_update_xsrc(phb); +} + static void pnv_phb4_err_reg_reset(PnvPHB4 *phb) { STICKY_RST(PHB_ERR_STATUS, 0, PPC_BITMASK(0, 33)); @@ -2000,10 +2007,11 @@ static void pnv_phb4_reset(Object *obj, ResetType t= ype) PnvPHB4 *phb =3D PNV_PHB4(obj); =20 pnv_phb4_pbl_core_reset(phb); + + pnv_phb4_xsrc_reset(phb); pnv_phb4_err_reg_reset(phb); pnv_phb4_pcie_stack_reg_reset(phb); pnv_phb4_regb_err_reg_reset(phb); - phb->regs[PHB_PCIE_CRESET >> 3] =3D 0xE000000000000000; } =20 static void pnv_phb4_instance_init(Object *obj) @@ -2080,8 +2088,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error = **errp) return; } =20 - pnv_phb4_update_xsrc(phb); - phb->qirqs =3D qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_= irqs); =20 pnv_phb4_xscom_realize(phb); --=20 2.47.3