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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Cc:To:In-Reply-To:References:Message-Id:Content-Transfer-Encoding: Content-Type:MIME-Version:Subject:Date:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=21vQG7vaneBGja49Q9ttUYUjtDN4zWdrOelgdFYyL/Y=; b=CS781HnCbyK0sZs imXPkdopFS6z25237kSo8O9/KAYL1Ew+YJDxQGuaDSJLLWixg/GL8uuIxo/mD9KhEZpbZk52CvBzE rrgu9XLjwER1UnDuFafGLNE4V3h3fq6GLchNl2Y80eowBMXPaMxKlWLLq84mijT9v9yZrP0OwzYx2 xU=; Date: Thu, 05 Mar 2026 23:54:20 +0100 Subject: [PATCH v6 1/3] hppa: Introduce HPPACPUDef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-hppa-c3600-v6-1-d51526e5269c@rev.ng> References: <20260305-hppa-c3600-v6-0-d51526e5269c@rev.ng> In-Reply-To: <20260305-hppa-c3600-v6-0-d51526e5269c@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772751314; l=9903; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=bP5w4Uw4mtobEQawfD2dhbdBX6swNEHwuIIjzpmZsR0=; b=B3FVtHh1uF0UVfAKvZC+Xun0kRW2I4Nu7SLvGWJGrP7Dap4BCxBhungJ1MJDB64smyXMgtcBs 6ytxbUfDRPQBSApOcYxBmx8eA+80BxsdLtfyGv7ohOk7/n/6i211VPm X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772751108993154100 Restructures the CPU class heirarchy to clarify model names and allow for per-model configuration options via HPPACPUDef. 32-bit HPPA is assumed to run a PA-7300LC, and 64-bit assumed to run a PA-8700. A new PA-8500 model is added, which will later be used by the A400 machine. All CPU models are made into children of the now abstract TYPE_HPPA_CPU base class. Two fields are added to HPPACPUDef describing the size of the physical address space, and whether or not the CPU uses the PA-RISC 2.0 architecture. The latter was previously a field in CPUHPPAState. phys_addr_bits is currently set but unused, and will be used in the following commit. Likewise, PA-8700 is moved to use 44 bit physical addresses in a followup commit to not break bisection. References to "hppa/hppa64" models in test cases are also updated. Reviewed-by: Helge Deller Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/hppa/cpu-qom.h | 8 ++++++- target/hppa/cpu.h | 24 ++++++++++++++++---- hw/hppa/machine.c | 21 ++++++++++------- linux-user/hppa/elfload.c | 2 +- target/hppa/cpu.c | 50 +++++++++++++++++++++++++++++++------= ---- tests/qtest/machine-none-test.c | 2 +- 6 files changed, 80 insertions(+), 27 deletions(-) diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index 5c454bf543..7541c25b3d 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -23,7 +23,13 @@ #include "hw/core/cpu.h" =20 #define TYPE_HPPA_CPU "hppa-cpu" -#define TYPE_HPPA64_CPU "hppa64-cpu" + +#define HPPA_CPU_TYPE_SUFFIX "-" TYPE_HPPA_CPU +#define HPPA_CPU_TYPE_NAME(name) (name HPPA_CPU_TYPE_SUFFIX) + +#define TYPE_HPPA_CPU_PA_7300LC HPPA_CPU_TYPE_NAME("pa-7300lc") +#define TYPE_HPPA_CPU_PA_8500 HPPA_CPU_TYPE_NAME("pa-8500") +#define TYPE_HPPA_CPU_PA_8700 HPPA_CPU_TYPE_NAME("pa-8700") =20 OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) =20 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 092e647ccf..43b4882fb4 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -270,8 +270,6 @@ typedef struct CPUArchState { /* Fields up to this point are cleared by a CPU reset */ struct {} end_reset_fields; =20 - bool is_pa20; - target_ulong kernel_entry; /* Linux kernel was loaded here */ target_ulong cmdline_or_bootorder; target_ulong initrd_base, initrd_end; @@ -290,6 +288,18 @@ struct ArchCPU { QEMUTimer *alarm_timer; }; =20 +/** + * HPPACPUDef: + * @phys_addr_bits: Number of bits in the physical address space. + * @is_pa20: Whether the CPU model follows the PA-RISC 2.0 or 1.1 spec. + * + * Configuration options for a HPPA CPU model. + */ +typedef struct HPPACPUDef { + uint8_t phys_addr_bits; + bool is_pa20; +} HPPACPUDef; + /** * HPPACPUClass: * @parent_realize: The parent class' realize handler. @@ -302,11 +312,17 @@ struct HPPACPUClass { =20 DeviceRealize parent_realize; ResettablePhases parent_phases; + const HPPACPUDef *def; }; =20 -static inline bool hppa_is_pa20(const CPUHPPAState *env) +static inline const HPPACPUDef *hppa_def(CPUHPPAState *env) +{ + return HPPA_CPU_GET_CLASS(env_cpu(env))->def; +} + +static inline bool hppa_is_pa20(CPUHPPAState *env) { - return env->is_pa20; + return hppa_def(env)->is_pa20; } =20 static inline int HPPA_BTLB_ENTRIES(CPUHPPAState *env) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index f55e84529f..5d0d4de09e 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -801,13 +801,13 @@ static void hppa_machine_common_class_init(ObjectClas= s *oc, const void *data) static void HP_B160L_machine_init_class_init(ObjectClass *oc, const void *= data) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA_CPU, + TYPE_HPPA_CPU_PA_7300LC, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP B160L workstation"; - mc->default_cpu_type =3D TYPE_HPPA_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_7300LC; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_B160L_init; mc->is_default =3D true; @@ -817,13 +817,13 @@ static void HP_B160L_machine_init_class_init(ObjectCl= ass *oc, const void *data) static void HP_C3700_machine_init_class_init(ObjectClass *oc, const void *= data) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, + TYPE_HPPA_CPU_PA_8700, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP C3700 workstation"; - mc->default_cpu_type =3D TYPE_HPPA64_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_8700; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_C3700_init; mc->max_cpus =3D HPPA_MAX_CPUS; @@ -833,13 +833,13 @@ static void HP_C3700_machine_init_class_init(ObjectCl= ass *oc, const void *data) static void HP_A400_machine_init_class_init(ObjectClass *oc, const void *d= ata) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA64_CPU, + TYPE_HPPA_CPU_PA_8500, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP A400-44 workstation"; - mc->default_cpu_type =3D TYPE_HPPA64_CPU; + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_8500; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_A400_init; mc->max_cpus =3D HPPA_MAX_CPUS; @@ -849,13 +849,18 @@ static void HP_A400_machine_init_class_init(ObjectCla= ss *oc, const void *data) static void HP_715_machine_init_class_init(ObjectClass *oc, const void *da= ta) { static const char * const valid_cpu_types[] =3D { - TYPE_HPPA_CPU, + TYPE_HPPA_CPU_PA_7300LC, NULL }; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "HP 715/64 workstation"; - mc->default_cpu_type =3D TYPE_HPPA_CPU; + /* + * Although the 715 workstation should use a 7100LC, it can be safely + * modeled as a 7300LC as the difference is a moving of the L1 data ca= che + * to on-chip. + */ + mc->default_cpu_type =3D TYPE_HPPA_CPU_PA_7300LC; mc->valid_cpu_types =3D valid_cpu_types; mc->init =3D machine_HP_715_init; /* can only support up to max. 8 CPUs due inventory major numbers */ diff --git a/linux-user/hppa/elfload.c b/linux-user/hppa/elfload.c index 4600708702..7f7ece6dc1 100644 --- a/linux-user/hppa/elfload.c +++ b/linux-user/hppa/elfload.c @@ -8,7 +8,7 @@ =20 const char *get_elf_cpu_model(uint32_t eflags) { - return "hppa"; + return "pa-7300lc"; } =20 const char *get_elf_platform(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 714f3bbdaf..cc755da8be 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -203,13 +203,6 @@ static void hppa_cpu_realizefn(DeviceState *dev, Error= **errp) tcg_cflags_set(cs, CF_PCREL); } =20 -static void hppa_cpu_initfn(Object *obj) -{ - CPUHPPAState *env =3D cpu_env(CPU(obj)); - - env->is_pa20 =3D !!object_dynamic_cast(obj, TYPE_HPPA64_CPU); -} - static void hppa_cpu_reset_hold(Object *obj, ResetType type) { HPPACPUClass *scc =3D HPPA_CPU_GET_CLASS(obj); @@ -236,9 +229,14 @@ static void hppa_cpu_reset_hold(Object *obj, ResetType= type) =20 static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) { - g_autofree char *typename =3D g_strconcat(cpu_model, "-cpu", NULL); + ObjectClass *oc; + char *typename; =20 - return object_class_by_name(typename); + typename =3D g_strdup_printf(HPPA_CPU_TYPE_NAME("%s"), cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + + return oc; } =20 #ifndef CONFIG_USER_ONLY @@ -279,6 +277,14 @@ static const TCGCPUOps hppa_tcg_ops =3D { #endif /* !CONFIG_USER_ONLY */ }; =20 +static void hppa_cpu_class_base_init(ObjectClass *oc, const void *data) +{ + HPPACPUClass *acc =3D HPPA_CPU_CLASS(oc); + /* Make sure all CPU models define a HPPACPUDef */ + g_assert(!object_class_is_abstract(oc) && data !=3D NULL); + acc->def =3D data; +} + static void hppa_cpu_class_init(ObjectClass *oc, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); @@ -313,14 +319,34 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .parent =3D TYPE_CPU, .instance_size =3D sizeof(HPPACPU), .instance_align =3D __alignof(HPPACPU), - .instance_init =3D hppa_cpu_initfn, - .abstract =3D false, + .abstract =3D true, .class_size =3D sizeof(HPPACPUClass), .class_init =3D hppa_cpu_class_init, + .class_base_init =3D hppa_cpu_class_base_init, + }, + { + .name =3D TYPE_HPPA_CPU_PA_7300LC, + .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 32, + .is_pa20 =3D false, + }, + }, + { + .name =3D TYPE_HPPA_CPU_PA_8500, + .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, { - .name =3D TYPE_HPPA64_CPU, + .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, + .class_data =3D &(const HPPACPUDef) { + .phys_addr_bits =3D 40, + .is_pa20 =3D true, + }, }, }; =20 diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index c1e22dcecc..bafd7d660e 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -47,7 +47,7 @@ static struct arch2cpu cpus_map[] =3D { { "tricore", "tc1796" }, { "xtensa", "dc233c" }, { "xtensaeb", "fsf" }, - { "hppa", "hppa" }, + { "hppa", "pa-7300lc" }, { "riscv64", "rv64" }, { "riscv32", "rv32" }, { "rx", "rx62n" }, --=20 2.52.0 From nobody Sat Apr 11 21:33:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1772751138; cv=none; d=zohomail.com; s=zohoarc; b=KPQlwTVTcr6979WsiwYfkoaY3nDmJvrAeiPEVG64XM1c7mVC8oCIi/TckyI2pxMzafo49UsJqS/6RR2PGuNJh314Xi8j3NSA/VES0Azo4pRzo8e6edsEvJIC2SzTaxiIiPL4vP4hKEz5xn4+4/GlPYUBZMye2Zc6WMF+lq6iSSQ= ARC-Message-Signature: i=1; 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Date: Thu, 05 Mar 2026 23:54:21 +0100 Subject: [PATCH v6 2/3] hppa: Get physical address space bits from HPPACPUDef MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260305-hppa-c3600-v6-2-d51526e5269c@rev.ng> References: <20260305-hppa-c3600-v6-0-d51526e5269c@rev.ng> In-Reply-To: <20260305-hppa-c3600-v6-0-d51526e5269c@rev.ng> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Helge Deller , Anton Johansson X-Developer-Signature: v=1; a=ed25519-sha256; t=1772751314; l=8538; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=pzPW+/suWpFmxbJncwZH5AV/5sxO/vSuDIBoNyJ+3E4=; b=F3lpF9XxeO8S1Oj7bcxT9dGVmWqEELdQNwBxqvxz+MzmvDq9ZCD+2Y9H5CvhkxZ7EJe8519AY 7rXAVOlPVvtAxY2jz5Vf6N8dRfV9whJJU8qnG6sunYhixUAexBo9pfi X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772751140691158500 Signed-off-by: Anton Johansson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/pci-host/astro.h | 2 ++ target/hppa/cpu.h | 11 ++++++++--- hw/hppa/machine.c | 15 ++++++++++----- hw/pci-host/astro.c | 8 +++++++- target/hppa/cpu.c | 5 +++++ target/hppa/mem_helper.c | 39 +++++++++++---------------------------- 6 files changed, 43 insertions(+), 37 deletions(-) diff --git a/include/hw/pci-host/astro.h b/include/hw/pci-host/astro.h index 832125a05a..fce052c9f8 100644 --- a/include/hw/pci-host/astro.h +++ b/include/hw/pci-host/astro.h @@ -82,6 +82,8 @@ struct AstroState { uint64_t tlb_tcnfg; uint64_t tlb_pdir_base; =20 + uint8_t phys_addr_bits; + struct ElroyState *elroy[ELROY_NUM]; =20 MemoryRegion this_mem; diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 43b4882fb4..7d47afe8ef 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -320,6 +320,11 @@ static inline const HPPACPUDef *hppa_def(CPUHPPAState = *env) return HPPA_CPU_GET_CLASS(env_cpu(env))->def; } =20 +static inline uint8_t hppa_phys_addr_bits(CPUHPPAState *env) +{ + return hppa_def(env)->phys_addr_bits; +} + static inline bool hppa_is_pa20(CPUHPPAState *env) { return hppa_def(env)->is_pa20; @@ -352,9 +357,9 @@ static inline vaddr hppa_form_gva(CPUHPPAState *env, ui= nt64_t spc, return hppa_form_gva_mask(env->gva_offset_mask, spc, off); } =20 -hwaddr hppa_abs_to_phys_pa1x(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr); -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr); +hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr); +hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr); =20 /* * Since PSW_{I,CB} will never need to be in tb->flags, reuse them. diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 5d0d4de09e..6b69a304c2 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -179,19 +179,21 @@ static uint64_t linux_kernel_virt_to_phys(void *opaqu= e, uint64_t addr) return addr; } =20 +static HPPACPU *cpu[HPPA_MAX_CPUS]; +static uint64_t firmware_entry; + static uint64_t translate_pa10(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa1x(addr); + const uint8_t pa_bits =3D hppa_phys_addr_bits(&cpu[0]->env); + return hppa_abs_to_phys_pa1x(pa_bits, addr); } =20 static uint64_t translate_pa20(void *dummy, uint64_t addr) { - return hppa_abs_to_phys_pa2_w0(addr); + const uint8_t pa_bits =3D hppa_phys_addr_bits(&cpu[0]->env); + return hppa_abs_to_phys_pa2_w0(pa_bits, addr); } =20 -static HPPACPU *cpu[HPPA_MAX_CPUS]; -static uint64_t firmware_entry; - static void fw_cfg_boot_set(void *opaque, const char *boot_device, Error **errp) { @@ -685,6 +687,9 @@ static AstroState *astro_init(void) DeviceState *dev; =20 dev =3D qdev_new(TYPE_ASTRO_CHIP); + object_property_set_int(OBJECT(dev), "phys-addr-bits", + hppa_phys_addr_bits(&cpu[0]->env), + &error_abort); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); =20 return ASTRO_CHIP(dev); diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 00a904277c..626aa9ce22 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -303,7 +303,7 @@ static IOMMUTLBEntry astro_translate_iommu(IOMMUMemoryR= egion *iommu, * language which not-coincidentally matches the PSW.W=3D0 mapping. */ if (addr <=3D UINT32_MAX) { - entry =3D hppa_abs_to_phys_pa2_w0(addr); + entry =3D hppa_abs_to_phys_pa2_w0(s->phys_addr_bits, addr); } else { entry =3D addr; } @@ -910,6 +910,10 @@ static void astro_realize(DeviceState *obj, Error **er= rp) } } =20 +static const Property astro_props[] =3D { + DEFINE_PROP_UINT8("phys-addr-bits", AstroState, phys_addr_bits, 32), +}; + static void astro_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -922,6 +926,8 @@ static void astro_class_init(ObjectClass *klass, const = void *data) * be created without that hardware */ dc->user_creatable =3D false; + + device_class_set_props(dc, astro_props); } =20 static const TypeInfo astro_chip_info =3D { diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index cc755da8be..5895b9d7c0 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -283,6 +283,11 @@ static void hppa_cpu_class_base_init(ObjectClass *oc, = const void *data) /* Make sure all CPU models define a HPPACPUDef */ g_assert(!object_class_is_abstract(oc) && data !=3D NULL); acc->def =3D data; + /* + * Verify assumptions made in hppa_abs_to_phys_pa2_w1() on the size + * of the physical address space. + */ + g_assert(acc->def->phys_addr_bits <=3D 54); } =20 static void hppa_cpu_class_init(ObjectClass *oc, const void *data) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 9199d1e06a..a4b382069d 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -29,29 +29,12 @@ #include "hw/core/cpu.h" #include "trace.h" =20 -/* - * 64-bit (PA-RISC 2.0) machines are assumed to run PA-8700, and 32-bit - * machines 7300LC. This should give 44 and 32 bits of physical address - * space respectively. - * - * CPU model Physical address space bits - * PA-7000--7300LC 32 - * PA-8000--8600 40 - * PA-8700--8900 44 - * - * FIXME: However, the SeaBIOS firmware that is that tested against - * uses 40-bit physical addresses, despite supposedly running a C3700 - * with a PA-8700 cpu, so use 40-bits for 64-bit. - */ -#define HPPA_PHYS_ADDR_SPACE_BITS_PA20 40 -#define HPPA_PHYS_ADDR_SPACE_BITS_PA1X 32 - -hwaddr hppa_abs_to_phys_pa1x(vaddr addr) +hwaddr hppa_abs_to_phys_pa1x(uint8_t phys_addr_bits, vaddr addr) { - return extract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA1X); + return extract64(addr, 0, phys_addr_bits); } =20 -hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w1(uint8_t phys_addr_bits, vaddr addr) { /* * Figure H-8 "62-bit Absolute Accesses when PSW W-bit is 1" describes @@ -64,11 +47,10 @@ hwaddr hppa_abs_to_phys_pa2_w1(vaddr addr) * Since the supported physical address space is below 54 bits, the * H-8 algorithm is moot and all that is left is to truncate. */ - QEMU_BUILD_BUG_ON(HPPA_PHYS_ADDR_SPACE_BITS_PA20 > 54); - return sextract64(addr, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + return sextract64(addr, 0, phys_addr_bits); } =20 -hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) +hwaddr hppa_abs_to_phys_pa2_w0(uint8_t phys_addr_bits, vaddr addr) { /* * See Figure H-10, "Absolute Accesses when PSW W-bit is 0", @@ -89,7 +71,7 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) * is what can be seen on physical machines too. */ addr =3D (uint32_t)addr; - addr |=3D -1ull << (HPPA_PHYS_ADDR_SPACE_BITS_PA20 - 4); + addr |=3D -1ull << (phys_addr_bits - 4); } return addr; } @@ -231,15 +213,16 @@ int hppa_get_physical_address(CPUHPPAState *env, vadd= r addr, int mmu_idx, =20 /* Virtual translation disabled. Map absolute to physical. */ if (MMU_IDX_MMU_DISABLED(mmu_idx)) { + const uint8_t phys_addr_bits =3D hppa_phys_addr_bits(env); switch (mmu_idx) { case MMU_ABS_W_IDX: - phys =3D hppa_abs_to_phys_pa2_w1(addr); + phys =3D hppa_abs_to_phys_pa2_w1(phys_addr_bits, addr); break; case MMU_ABS_IDX: if (hppa_is_pa20(env)) { - phys =3D hppa_abs_to_phys_pa2_w0(addr); + phys =3D hppa_abs_to_phys_pa2_w0(phys_addr_bits, addr); } else { - phys =3D hppa_abs_to_phys_pa1x(addr); + phys =3D hppa_abs_to_phys_pa1x(phys_addr_bits, addr); } break; default: @@ -580,7 +563,7 @@ static void itlbt_pa20(CPUHPPAState *env, target_ulong = r1, /* Align per the page size. */ ent->pa &=3D TARGET_PAGE_MASK << mask_shift; /* Ignore the bits beyond physical address space. */ - ent->pa =3D sextract64(ent->pa, 0, HPPA_PHYS_ADDR_SPACE_BITS_PA20); + ent->pa =3D sextract64(ent->pa, 0, hppa_phys_addr_bits(env)); =20 ent->t =3D extract64(r2, 61, 1); ent->d =3D extract64(r2, 60, 1); --=20 2.52.0 From nobody Sat Apr 11 21:33:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a=ed25519-sha256; t=1772751314; l=1705; i=anjo@rev.ng; s=20260210; h=from:subject:message-id; bh=QhCmR++fNiHVlaTqSGM+ku4d4Y2pUsErpEmJbt3vCb4=; b=IuhgzSqIkKDqRH6zgxaq4eqbTspGBdtPGGGG4aIOZXViPyo4DWZNj7LjnmfOMAY8gmHymbv0i CaLybnkcnXUBMTRpt850COyMiwdOqqLXKKXslRtS3Vj9GLMMeb6f/sn X-Developer-Key: i=anjo@rev.ng; a=ed25519; pk=dKsZvj/g3kgDxnV1/SWg8a0YNGSpWtFGNsWIepQYKow= Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.892, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.622, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via qemu development Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1772751137260154100 This is in line with the PA-8700 specification which demands 44 bits. However, this change breaks the SeaBIOS functional tests as the firmware assumes 40 bit physical addresses. Therefore, change the functional tests to instead run on an A400 which has the expected physical address space size. Reviewed-by: Helge Deller Signed-off-by: Anton Johansson --- target/hppa/cpu.c | 2 +- tests/functional/hppa/test_seabios.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 5895b9d7c0..92027d129a 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -349,7 +349,7 @@ static const TypeInfo hppa_cpu_type_infos[] =3D { .name =3D TYPE_HPPA_CPU_PA_8700, .parent =3D TYPE_HPPA_CPU, .class_data =3D &(const HPPACPUDef) { - .phys_addr_bits =3D 40, + .phys_addr_bits =3D 44, .is_pa20 =3D true, }, }, diff --git a/tests/functional/hppa/test_seabios.py b/tests/functional/hppa/= test_seabios.py index 661b2464e1..bdb9d534ef 100755 --- a/tests/functional/hppa/test_seabios.py +++ b/tests/functional/hppa/test_seabios.py @@ -12,7 +12,7 @@ class HppaSeabios(QemuSystemTest): =20 timeout =3D 5 - MACH_BITS =3D {'B160L': 32, 'C3700': 64} + MACH_BITS =3D {'B160L': 32, 'A400': 64} =20 def boot_seabios(self): mach =3D self.machine @@ -28,7 +28,7 @@ def test_hppa_32(self): self.boot_seabios() =20 def test_hppa_64(self): - self.set_machine('C3700') + self.set_machine('A400') self.boot_seabios() =20 if __name__ =3D=3D '__main__': --=20 2.52.0