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a="73909326" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="73909326" X-CSE-ConnectionGUID: 3kSr4sIlSxGMip9pgPb8jg== X-CSE-MsgGUID: 7WJ63Z9eQkepkTpA1uHA1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="214542808" From: Zide Chen To: qemu-devel@nongnu.org, kvm@vger.kernel.org, Paolo Bonzini , Zhao Liu , Peter Xu , Fabiano Rosas , Sandipan Das Cc: Xiaoyao Li , Dongli Zhang , Dapeng Mi , Zide Chen Subject: [PATCH V3 06/13] target/i386: Increase MSR_BUF_SIZE and split KVM_[GET/SET]_MSRS calls Date: Wed, 4 Mar 2026 10:07:05 -0800 Message-ID: <20260304180713.360471-7-zide.chen@intel.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260304180713.360471-1-zide.chen@intel.com> References: <20260304180713.360471-1-zide.chen@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.16; envelope-from=zide.chen@intel.com; helo=mgamail.intel.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.703, RCVD_IN_VALIDITY_SAFE_BLOCKED=1.386, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1772648243192158500 Content-Type: text/plain; charset="utf-8" Newer Intel server CPUs support a large number of PMU MSRs. Currently, QEMU allocates cpu->kvm_msr_buf as a single-page buffer, which is not sufficient to hold all possible MSRs. Increase MSR_BUF_SIZE to 8192 bytes, providing space for up to 511 MSRs. This is sufficient even for the theoretical worst case, such as architectural LBR with a depth of 64. KVM_[GET/SET]_MSRS is limited to 255 MSRs per call. Raising this limit to 511 would require changes in KVM and would introduce backward compatibility issues. Instead, split requests into multiple KVM_[GET/SET]_MSRS calls when the number of MSRs exceeds the API limit. Signed-off-by: Zide Chen Reviewed-by: Dapeng Mi --- v3: - Address Dapeng's comments. --- target/i386/kvm/kvm.c | 110 +++++++++++++++++++++++++++++++++++------- 1 file changed, 92 insertions(+), 18 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 39a67c58ac22..4ba54151320f 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -97,9 +97,12 @@ #define KVM_APIC_BUS_CYCLE_NS 1 #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) =20 -/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus - * 255 kvm_msr_entry structs */ -#define MSR_BUF_SIZE 4096 +/* A 8192-byte buffer can hold the 8-byte kvm_msrs header, plus + * 511 kvm_msr_entry structs */ +#define MSR_BUF_SIZE 8192 + +/* Maximum number of MSRs in one single KVM_[GET/SET]_MSRS call. */ +#define KVM_MAX_IO_MSRS 255 =20 typedef bool QEMURDMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t *val); typedef bool QEMUWRMSRHandler(X86CPU *cpu, uint32_t msr, uint64_t val); @@ -4016,21 +4019,99 @@ static void kvm_msr_entry_add_perf(X86CPU *cpu, Fea= tureWordArray f) } } =20 -static int kvm_buf_set_msrs(X86CPU *cpu) +static int __kvm_buf_set_msrs(X86CPU *cpu, struct kvm_msrs *msrs) { - int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); + int ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, msrs); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx6= 4, (uint32_t)e->index, (uint64_t)e->data); } =20 - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); - return 0; + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int __kvm_buf_get_msrs(X86CPU *cpu, struct kvm_msrs *msrs) +{ + int ret; + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, msrs); + if (ret < 0) { + return ret; + } + + if (ret < msrs->nmsrs) { + struct kvm_msr_entry *e =3D &msrs->entries[ret]; + error_report("error: failed to get MSR 0x%" PRIx32, + (uint32_t)e->index); + } + + assert(ret =3D=3D msrs->nmsrs); + return ret; +} + +static int kvm_buf_set_or_get_msrs(X86CPU *cpu, bool is_write) +{ + struct kvm_msr_entry *entries =3D cpu->kvm_msr_buf->entries; + struct kvm_msrs *buf =3D NULL; + int current, remaining, ret =3D 0; + size_t buf_size; + + buf_size =3D KVM_MAX_IO_MSRS * sizeof(struct kvm_msr_entry) + + sizeof(struct kvm_msrs); + buf =3D g_malloc(buf_size); + + remaining =3D cpu->kvm_msr_buf->nmsrs; + current =3D 0; + while (remaining) { + size_t size; + + memset(buf, 0, buf_size); + + if (remaining > KVM_MAX_IO_MSRS) { + buf->nmsrs =3D KVM_MAX_IO_MSRS; + } else { + buf->nmsrs =3D remaining; + } + + size =3D buf->nmsrs * sizeof(entries[0]); + memcpy(buf->entries, &entries[current], size); + + if (is_write) { + ret =3D __kvm_buf_set_msrs(cpu, buf); + } else { + ret =3D __kvm_buf_get_msrs(cpu, buf); + } + + if (ret < 0) { + goto out; + } + + if (!is_write) + memcpy(&entries[current], buf->entries, size); + + current +=3D buf->nmsrs; + remaining -=3D buf->nmsrs; + } + +out: + g_free(buf); + return ret < 0 ? ret : cpu->kvm_msr_buf->nmsrs; +} + +static inline int kvm_buf_set_msrs(X86CPU *cpu) +{ + return kvm_buf_set_or_get_msrs(cpu, true); +} + +static inline int kvm_buf_get_msrs(X86CPU *cpu) +{ + return kvm_buf_set_or_get_msrs(cpu, false); } =20 static void kvm_init_msrs(X86CPU *cpu) @@ -4066,7 +4147,7 @@ static void kvm_init_msrs(X86CPU *cpu) if (has_msr_ucode_rev) { kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); } - assert(kvm_buf_set_msrs(cpu) =3D=3D 0); + kvm_buf_set_msrs(cpu); } =20 static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) @@ -4959,18 +5040,11 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); + ret =3D kvm_buf_get_msrs(cpu); if (ret < 0) { return ret; } =20 - if (ret < cpu->kvm_msr_buf->nmsrs) { - struct kvm_msr_entry *e =3D &cpu->kvm_msr_buf->entries[ret]; - error_report("error: failed to get MSR 0x%" PRIx32, - (uint32_t)e->index); - } - - assert(ret =3D=3D cpu->kvm_msr_buf->nmsrs); /* * MTRR masks: Each mask consists of 5 parts * a 10..0: must be zero --=20 2.53.0